Simulation Results

Simulation Results: kmac/unmasked

23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
79.18 %

code
65.69 %

assert
96.35 %

func
75.49 %

line
92.78 %

branch
87.43 %

cond
84.18 %

toggle
27.56 %

FSM
36.50 %

Validation stages

V1		100.00%
V2		68.97%
V2S		75.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	kmac_smoke	43.850s	11977.999us	1	1	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	1.070s	48.960us	1	1	100.00
csr_rw				1	1	100.00
	kmac_csr_rw	0.850s	37.064us	1	1	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	12.630s	851.889us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	5.270s	141.392us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	kmac_csr_mem_rw_with_rand_reset	2.270s	416.546us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	kmac_csr_rw	0.850s	37.064us	1	1	100.00
	kmac_csr_aliasing	5.270s	141.392us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	0.740s	41.359us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.410s	48.513us	1	1	100.00

20/29 passed

68.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				1	1	100.00
	kmac_long_msg_and_output	682.010s	12843.685us	1	1	100.00
burst_write				1	1	100.00
	kmac_burst_write	55.750s	1025.731us	1	1	100.00
test_vectors				8	8	100.00
	kmac_test_vectors_sha3_224	37.290s	11607.300us	1	1	100.00
	kmac_test_vectors_sha3_256	31.880s	6413.374us	1	1	100.00
	kmac_test_vectors_sha3_384	22.010s	1852.665us	1	1	100.00
	kmac_test_vectors_sha3_512	612.080s	147468.143us	1	1	100.00
	kmac_test_vectors_shake_128	2733.580s	138045.460us	1	1	100.00
	kmac_test_vectors_shake_256	223.090s	29710.350us	1	1	100.00
	kmac_test_vectors_kmac	2.370s	402.463us	1	1	100.00
	kmac_test_vectors_kmac_xof	1.990s	105.878us	1	1	100.00
sideload				1	1	100.00
	kmac_sideload	115.100s	7374.788us	1	1	100.00
app				0	1	0.00
	kmac_app	0.810s	15.109us	0	1	0.00
app_with_partial_data				0	1	0.00
	kmac_app_with_partial_data	5.030s	306.873us	0	1	0.00
entropy_refresh				0	1	0.00
	kmac_entropy_refresh	7.590s	1863.813us	0	1	0.00
error				0	1	0.00
	kmac_error	28.880s	677.019us	0	1	0.00
key_error				0	1	0.00
	kmac_key_error	0.910s	130.630us	0	1	0.00
sideload_invalid				0	1	0.00
	kmac_sideload_invalid	0.960s	12.987us	0	1	0.00
edn_timeout_error				1	1	100.00
	kmac_edn_timeout_error	12.130s	4472.558us	1	1	100.00
entropy_mode_error				1	1	100.00
	kmac_entropy_mode_error	10.030s	3067.468us	1	1	100.00
entropy_ready_error				0	1	0.00
	kmac_entropy_ready_error	1.240s	198.598us	0	1	0.00
lc_escalation				0	1	0.00
	kmac_lc_escalation	0.820s	33.061us	0	1	0.00
stress_all				0	1	0.00
	kmac_stress_all	9.860s	2767.542us	0	1	0.00
intr_test				1	1	100.00
	kmac_intr_test	0.850s	60.592us	1	1	100.00
alert_test				1	1	100.00
	kmac_alert_test	0.830s	57.563us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	kmac_tl_errors	1.870s	70.503us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	kmac_tl_errors	1.870s	70.503us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	kmac_csr_hw_reset	1.070s	48.960us	1	1	100.00
	kmac_csr_rw	0.850s	37.064us	1	1	100.00
	kmac_csr_aliasing	5.270s	141.392us	1	1	100.00
	kmac_same_csr_outstanding	1.850s	93.663us	1	1	100.00
tl_d_partial_access				4	4	100.00
	kmac_csr_hw_reset	1.070s	48.960us	1	1	100.00
	kmac_csr_rw	0.850s	37.064us	1	1	100.00
	kmac_csr_aliasing	5.270s	141.392us	1	1	100.00
	kmac_same_csr_outstanding	1.850s	93.663us	1	1	100.00

V2S

6/8 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				1	1	100.00
	kmac_shadow_reg_errors	1.860s	415.035us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	kmac_shadow_reg_errors	1.860s	415.035us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	kmac_shadow_reg_errors	1.860s	415.035us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	kmac_shadow_reg_errors	1.860s	415.035us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	kmac_shadow_reg_errors_with_csr_rw	2.270s	202.896us	1	1	100.00
tl_intg_err				2	2	100.00
	kmac_sec_cm	49.090s	6453.330us	1	1	100.00
	kmac_tl_intg_err	2.340s	222.701us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	kmac_tl_intg_err	2.340s	222.701us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				0	1	0.00
	kmac_lc_escalation	0.820s	33.061us	0	1	0.00
sec_cm_sw_key_key_masking				1	1	100.00
	kmac_smoke	43.850s	11977.999us	1	1	100.00
sec_cm_key_sideload				1	1	100.00
	kmac_sideload	115.100s	7374.788us	1	1	100.00
sec_cm_cfg_shadowed_config_shadow				1	1	100.00
	kmac_shadow_reg_errors	1.860s	415.035us	1	1	100.00
sec_cm_fsm_sparse				1	1	100.00
	kmac_sec_cm	49.090s	6453.330us	1	1	100.00
sec_cm_ctr_redun				1	1	100.00
	kmac_sec_cm	49.090s	6453.330us	1	1	100.00
sec_cm_packer_ctr_redun				1	1	100.00
	kmac_sec_cm	49.090s	6453.330us	1	1	100.00
sec_cm_cfg_shadowed_config_regwen				1	1	100.00
	kmac_smoke	43.850s	11977.999us	1	1	100.00
sec_cm_fsm_global_esc				0	1	0.00
	kmac_lc_escalation	0.820s	33.061us	0	1	0.00
sec_cm_fsm_local_esc				1	1	100.00
	kmac_sec_cm	49.090s	6453.330us	1	1	100.00
sec_cm_absorbed_ctrl_mubi				0	1	0.00
	kmac_mubi	4.120s	621.357us	0	1	0.00
sec_cm_sw_cmd_ctrl_sparse				1	1	100.00
	kmac_smoke	43.850s	11977.999us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	kmac_stress_all_with_rand_reset	54.700s	43062.230us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [] vs []) Mismatch between unmasked_digest[] and dpi_digest[*]				7 test runs
	kmac_sideload_invalid	25561308608629465724758838512233784851796170000782807418377074815498100597076	76	UVM_INFO @ 12987367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app	37972521210387447598797795260657150585921191097134852036983003776489444301946	77	UVM_INFO @ 15109428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app_with_partial_data	514158562931668744619185271427406201562836486672101903348111576662305961868	79	UVM_INFO @ 306872976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_refresh	18458505497149586523829827722994535727907460655923606859075515696303979358060	81	UVM_INFO @ 1863813241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_error	59094465569680905257259622450727187191766446360747406391709777540781889094673	96	UVM_INFO @ 677018767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_ready_error	103181280640367741800880237143279993340974072834372907024865641633892671015173	77	UVM_INFO @ 198597689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_lc_escalation	21510796063179214423114930417765208806037138656402434516359623228203901744063	77	UVM_INFO @ 33060564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err)				2 test runs
	kmac_mubi	29551052510547649512779519835668226499497029285584938528412652368011851144064	79	UVM_INFO @ 621356686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	32633900099386496346151134963867765069287613054418531683863235766491557843318	89	UVM_INFO @ 2767542163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))'				1 test run
	kmac_key_error	38407768958396537598104073921185365962537393727440386328044479494088616301229	78	UVM_ERROR @ 130629961 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 130629961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	kmac_stress_all_with_rand_reset	14301870389585188224714075590996106817702584558474983357721499908082333556906	155	UVM_INFO @ 43062230465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---