Simulation Results: lc_ctrl/volatile_unlock_disabled

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 84.07 %
  • assert
  • 94.13 %
  • func
  • 94.13 %
  • line
  • 97.24 %
  • branch
  • 93.56 %
  • cond
  • 79.29 %
  • toggle
  • 85.75 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.440s 29.549us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.880s 191.077us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.980s 15.272us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.640s 392.978us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 41.542us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.390s 121.359us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.980s 15.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 41.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.020s 57.954us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.770s 472.086us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 39.927us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.730s 103.887us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.140s 340.951us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_prog_failure 2.730s 103.887us 1 1 100.00
lc_ctrl_errors 5.140s 340.951us 1 1 100.00
lc_ctrl_security_escalation 8.220s 393.101us 1 1 100.00
lc_ctrl_jtag_state_failure 19.210s 1712.715us 1 1 100.00
lc_ctrl_jtag_prog_failure 12.490s 675.597us 1 1 100.00
lc_ctrl_jtag_errors 30.410s 1490.244us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.210s 289.262us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.790s 2034.350us 1 1 100.00
lc_ctrl_jtag_prog_failure 12.490s 675.597us 1 1 100.00
lc_ctrl_jtag_errors 30.410s 1490.244us 1 1 100.00
lc_ctrl_jtag_access 3.510s 167.595us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.030s 2146.364us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.530s 1002.484us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.340s 806.713us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.480s 3670.608us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.520s 1204.765us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.920s 107.410us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.220s 721.853us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 210.722us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.290s 566.863us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.980s 153.815us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 111.480s 43020.761us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.050s 69.847us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.880s 39.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.880s 39.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 191.077us 1 1 100.00
lc_ctrl_csr_rw 0.980s 15.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 41.542us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 230.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 191.077us 1 1 100.00
lc_ctrl_csr_rw 0.980s 15.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.830s 41.542us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 230.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
lc_ctrl_tl_intg_err 2.460s 124.854us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.460s 124.854us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.770s 472.086us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.300s 320.297us 1 1 100.00
lc_ctrl_sec_cm 7.570s 955.090us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.220s 393.101us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.020s 57.954us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.790s 2034.350us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.260s 1394.711us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.260s 1394.711us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.010s 1186.898us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 1689.275us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.230s 1689.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.960s 1398.594us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 7853564813259238586028413749372833546396059679010665409448438310361652474034 211
UVM_INFO @ 1398593881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---