Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.95 %
  • code
  • 84.52 %
  • assert
  • 94.55 %
  • func
  • 93.77 %
  • line
  • 97.13 %
  • branch
  • 93.52 %
  • cond
  • 79.41 %
  • toggle
  • 87.10 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.660s 51.257us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.040s 18.315us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 63.208us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.500s 410.730us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 26.743us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 38.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 63.208us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 26.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.440s 349.254us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.280s 1793.193us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 37.789us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.990s 133.488us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.550s 1797.086us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_prog_failure 1.990s 133.488us 1 1 100.00
lc_ctrl_errors 10.550s 1797.086us 1 1 100.00
lc_ctrl_security_escalation 6.430s 540.503us 1 1 100.00
lc_ctrl_jtag_state_failure 14.270s 3220.104us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.820s 649.822us 1 1 100.00
lc_ctrl_jtag_errors 27.840s 3715.594us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.790s 897.968us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.210s 1796.374us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.820s 649.822us 1 1 100.00
lc_ctrl_jtag_errors 27.840s 3715.594us 1 1 100.00
lc_ctrl_jtag_access 6.940s 1107.837us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.550s 8264.752us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.840s 187.201us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.900s 259.975us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.490s 2407.716us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.650s 567.333us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.370s 32.858us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.720s 88.178us 1 1 100.00
lc_ctrl_jtag_alert_test 0.830s 163.908us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 20.040s 2322.592us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 47.164us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 53.600s 5273.972us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.820s 196.728us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.390s 138.713us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.390s 138.713us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 18.315us 1 1 100.00
lc_ctrl_csr_rw 0.870s 63.208us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 26.743us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 78.238us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 18.315us 1 1 100.00
lc_ctrl_csr_rw 0.870s 63.208us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 26.743us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.230s 78.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
lc_ctrl_tl_intg_err 3.260s 242.884us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.260s 242.884us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.280s 1793.193us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.500s 1311.072us 1 1 100.00
lc_ctrl_sec_cm 7.910s 901.407us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.430s 540.503us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.440s 349.254us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.210s 1796.374us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.090s 4336.149us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.090s 4336.149us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.580s 713.074us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.630s 302.522us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.630s 302.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 9.040s 2253.228us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 30636269874717063729252528862630621145945897747351805241665496851103843659326 317
UVM_INFO @ 2253228434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---