Simulation Results: otp_ctrl

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.40 %
  • code
  • 78.82 %
  • assert
  • 94.51 %
  • func
  • 73.86 %
  • line
  • 88.62 %
  • branch
  • 83.73 %
  • cond
  • 90.32 %
  • toggle
  • 85.79 %
  • FSM
  • 45.66 %
Validation stages
V1
88.89%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.420s 203.214us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.910s 117.068us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.760s 58.983us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.710s 2715.758us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.290s 143.150us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.400s 36.679us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.760s 58.983us 1 1 100.00
otp_ctrl_csr_aliasing 2.290s 143.150us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.480s 562.007us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.820s 562.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 18.140s 6022.217us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.480s 223.492us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 12.740s 1171.083us 1 1 100.00
otp_ctrl_check_fail 8.120s 1048.342us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.840s 227.118us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 16.640s 663.319us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 24.590s 12929.644us 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 10.820s 740.257us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 6.410s 439.032us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 9.370s 7854.229us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 98.390s 16705.402us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.830s 612.813us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.920s 813.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.580s 831.625us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.580s 831.625us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 117.068us 1 1 100.00
otp_ctrl_csr_rw 1.760s 58.983us 1 1 100.00
otp_ctrl_csr_aliasing 2.290s 143.150us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.210s 214.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.910s 117.068us 1 1 100.00
otp_ctrl_csr_rw 1.760s 58.983us 1 1 100.00
otp_ctrl_csr_aliasing 2.290s 143.150us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.210s 214.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
otp_ctrl_tl_intg_err 12.630s 3383.573us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.630s 3383.573us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_macro_errs 6.410s 439.032us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_macro_errs 6.410s 439.032us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 12.690s 5866.765us 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.480s 223.492us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 8.120s 1048.342us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 5.650s 1035.443us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 99.020s 9604.248us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.840s 227.118us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.910s 950.350us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 6.410s 439.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 12.670s 8756.603us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.330s 26.087us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 2 test runs
otp_ctrl_stress_all_with_rand_reset 90391234788964071943698623521868366369167771731302190517894115725750224773597 92
UVM_INFO @ 26086597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 109735693779802167923732134980708877858454038348732411326670791697166217601251 92
UVM_INFO @ 36679461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---