Simulation Results: pwrmgr

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 91.36 %
  • assert
  • 98.17 %
  • func
  • 97.86 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.18 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 29.865us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.890s 34.731us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.820s 182.606us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.780s 201.301us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.950s 52.902us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 201.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.830s 161.530us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.830s 161.530us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.980s 90.396us 1 1 100.00
pwrmgr_lowpower_invalid 0.650s 45.324us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.900s 323.921us 1 1 100.00
pwrmgr_reset_invalid 0.720s 38.878us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.900s 323.921us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 90.935us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.640s 60.838us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.040s 117.042us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.580s 1249.471us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.610s 64.687us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.750s 47.695us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.750s 47.695us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.890s 34.731us 1 1 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 201.301us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 50.290us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.890s 34.731us 1 1 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 201.301us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 50.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.990s 210.543us 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.990s 210.543us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.990s 794.756us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.680s 90.935us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.910s 732.874us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.790s 53.299us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.660s 32.391us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.650s 642.851us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 54.633us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.630s 105.643us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.840s 119.436us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 25.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.790s 198.294us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.490s 8950.264us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep 1 test run
pwrmgr_reset_invalid 115292476478263847812351006296825355302895283468748615658834112933657540917240 125
UVM_INFO @ 38878233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---