Simulation Results: rom_ctrl/32kb

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 98.20 %
  • assert
  • 96.81 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.62 %
  • toggle
  • 94.63 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.320s 134.873us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.550s 364.724us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.590s 127.455us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.420s 385.917us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.130s 960.365us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.190s 309.796us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.590s 127.455us 1 1 100.00
rom_ctrl_csr_aliasing 3.130s 960.365us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.490s 123.755us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.480s 127.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.030s 428.745us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.270s 615.913us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.400s 389.207us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.100s 168.703us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.450s 123.938us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.450s 123.938us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.550s 364.724us 1 1 100.00
rom_ctrl_csr_rw 3.590s 127.455us 1 1 100.00
rom_ctrl_csr_aliasing 3.130s 960.365us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.610s 765.453us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.550s 364.724us 1 1 100.00
rom_ctrl_csr_rw 3.590s 127.455us 1 1 100.00
rom_ctrl_csr_aliasing 3.130s 960.365us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.610s 765.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.610s 2243.587us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
rom_ctrl_tl_intg_err 23.430s 707.126us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.320s 134.873us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.320s 134.873us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.320s 134.873us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 23.430s 707.126us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
rom_ctrl_kmac_err_chk 6.400s 389.207us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.020s 3228.875us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.610s 2243.587us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 204.980s 2421.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 33.400s 5000.625us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 35429561887148793572324199848359788770122934317916430282884843944309241271711 79
UVM_INFO @ 428745325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---