Simulation Results: rom_ctrl/64kb

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 96.80 %
  • assert
  • 97.24 %
  • func
  • 96.90 %
  • line
  • 99.19 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 94.80 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.090s 335.867us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.420s 212.231us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.840s 699.283us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.790s 1070.621us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 295.452us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.430s 311.528us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.840s 699.283us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 295.452us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.800s 254.918us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.670s 543.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.860s 271.748us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 21.290s 836.906us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.250s 722.918us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.780s 543.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.440s 1559.538us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.440s 1559.538us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.420s 212.231us 1 1 100.00
rom_ctrl_csr_rw 5.840s 699.283us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 295.452us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.320s 207.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.420s 212.231us 1 1 100.00
rom_ctrl_csr_rw 5.840s 699.283us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 295.452us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.320s 207.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.940s 4242.082us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
rom_ctrl_tl_intg_err 99.460s 2419.219us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.090s 335.867us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.090s 335.867us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.090s 335.867us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 99.460s 2419.219us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
rom_ctrl_kmac_err_chk 12.250s 722.918us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 98.280s 6770.854us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.940s 4242.082us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 244.510s 934.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 89.450s 3301.627us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 29151409092406713608715569429770781393897407062276646842562560022545357009467 79
UVM_INFO @ 271748397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---