Simulation Results: rstmgr

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 99.33 %
  • assert
  • 98.93 %
  • func
  • 96.02 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.58 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 266.906us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.900s 149.244us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 8.390s 2847.474us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.220s 219.077us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.100s 151.733us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.370s 576.794us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.330s 320.291us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.680s 1071.841us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.680s 1071.841us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.680s 1071.841us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.680s 1071.841us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 26.030s 12873.805us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.900s 74.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.340s 231.366us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.340s 231.366us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.900s 149.244us 1 1 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.909us 1 1 100.00
rstmgr_same_csr_outstanding 1.630s 267.583us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.900s 149.244us 1 1 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00
rstmgr_csr_aliasing 2.210s 413.909us 1 1 100.00
rstmgr_same_csr_outstanding 1.630s 267.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 24.120s 18680.895us 1 1 100.00
rstmgr_tl_intg_err 2.210s 852.786us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 24.120s 18680.895us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 24.120s 18680.895us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.210s 852.786us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.910s 118.314us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.870s 1416.408us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.040s 302.246us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 24.120s 18680.895us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 74.779us 1 1 100.00