Simulation Results: rv_timer

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 92.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.430s 1502.459us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 64.619us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.610s 46.974us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.830s 105.860us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.790s 35.298us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.830s 34.580us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.610s 46.974us 1 1 100.00
rv_timer_csr_aliasing 0.790s 35.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.880s 66.184us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.800s 143.836us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.580s 120.196us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.580s 120.196us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.210s 3582.887us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.580s 105.714us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.640s 15.925us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.420s 710.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.420s 710.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 64.619us 1 1 100.00
rv_timer_csr_rw 0.610s 46.974us 1 1 100.00
rv_timer_csr_aliasing 0.790s 35.298us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 31.829us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 64.619us 1 1 100.00
rv_timer_csr_rw 0.610s 46.974us 1 1 100.00
rv_timer_csr_aliasing 0.790s 35.298us 1 1 100.00
rv_timer_same_csr_outstanding 0.810s 31.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.820s 119.292us 1 1 100.00
rv_timer_tl_intg_err 1.220s 292.769us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.220s 292.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.590s 63.687us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.750s 304.146us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.600s 2959.554us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 59561607428460807503610823868883771739103659159091934423265299718944280184476 75
UVM_INFO @ 63686712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 17178738621739577263994818107419134068933962341635663425841187200239045790826 75
UVM_INFO @ 66183541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 90810636224875345025974497754869075238848336613201062619222362327113726081078 76
UVM_INFO @ 304146415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---