Simulation Results: spi_device/1r1w

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.27 %
  • code
  • 91.20 %
  • assert
  • 95.40 %
  • func
  • 72.22 %
  • line
  • 98.79 %
  • branch
  • 98.04 %
  • cond
  • 96.13 %
  • toggle
  • 73.68 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 64.630s 8776.232us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.820s 16.656us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 0.990s 19.844us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.860s 805.775us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.170s 109.248us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.220s 552.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 0.990s 19.844us 1 1 100.00
spi_device_csr_aliasing 5.170s 109.248us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.830s 20.247us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.710s 36.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.870s 51.904us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.660s 4.866us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.710s 4.285us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.480s 326.470us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.480s 326.470us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.770s 8588.066us 1 1 100.00
spi_device_tpm_sts_read 0.790s 12.351us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.840s 15.047us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.860s 1175.815us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.970s 591.059us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.970s 591.059us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 12.770s 25083.618us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 12.770s 25083.618us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 12.770s 25083.618us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 12.770s 25083.618us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 12.770s 25083.618us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.790s 1822.667us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.410s 888.347us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.410s 888.347us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.410s 888.347us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.340s 1555.118us 1 1 100.00
spi_device_read_buffer_direct 3.830s 307.917us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.410s 888.347us 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 123.090s 30718.253us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.670s 254.563us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.670s 254.563us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 13.670s 2300.250us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 64.630s 8776.232us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 28.110s 8207.427us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 58.450s 9902.141us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 11.099us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 12.982us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.350s 565.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.350s 565.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 16.656us 1 1 100.00
spi_device_csr_rw 0.990s 19.844us 1 1 100.00
spi_device_csr_aliasing 5.170s 109.248us 1 1 100.00
spi_device_same_csr_outstanding 3.370s 3195.965us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.820s 16.656us 1 1 100.00
spi_device_csr_rw 0.990s 19.844us 1 1 100.00
spi_device_csr_aliasing 5.170s 109.248us 1 1 100.00
spi_device_same_csr_outstanding 3.370s 3195.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.120s 250.146us 1 1 100.00
spi_device_tl_intg_err 11.090s 2570.653us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.090s 2570.653us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 3864859058022916568860593314264028206301426963802751494963401414131381817954 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 3706391 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 3706391 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[902])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 89462620388527876311331783396994899745486234891350200235884088050673920102805 76
UVM_ERROR @ 2037939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1e6 [111100110] vs 0x0 [0])
UVM_ERROR @ 2114939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21f [1000011111] vs 0x0 [0])
UVM_ERROR @ 2137939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b8 [1110111000] vs 0x0 [0])
UVM_ERROR @ 2191939 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x315 [1100010101] vs 0x0 [0])