Simulation Results: spi_host

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.84 %
  • code
  • 91.18 %
  • assert
  • 95.27 %
  • func
  • 89.08 %
  • block
  • 96.83 %
  • line
  • 98.59 %
  • branch
  • 93.05 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 18.000s 3609.752us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 19.453us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 29.197us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 290.255us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 166.654us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 29.197us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.673us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 40.437us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 51.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 33.377us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 48.805us 1 1 100.00
spi_host_error_cmd 2.000s 48.112us 1 1 100.00
spi_host_event 4.000s 642.169us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 172.925us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 172.925us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 172.925us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 89.000s 22127.305us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 57.627us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 30.471us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 172.925us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 172.925us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 18.000s 3609.752us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 18.000s 3609.752us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 22.000s 921.543us 1 1 100.00
spien 1 1 100.00
spi_host_spien 7.000s 3923.494us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 24.000s 5253.485us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 39.436us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 48.805us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 19.988us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.725us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 421.226us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 421.226us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.453us 1 1 100.00
spi_host_csr_rw 1.000s 29.197us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.673us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 114.599us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 19.453us 1 1 100.00
spi_host_csr_rw 1.000s 29.197us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.673us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 114.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 357.208us 1 1 100.00
spi_host_sec_cm 1.000s 122.139us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 357.208us 1 1 100.00