Simulation Results: sram_ctrl/main

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.46 %
  • code
  • 95.04 %
  • assert
  • 97.55 %
  • func
  • 93.80 %
  • block
  • 95.09 %
  • line
  • 95.72 %
  • branch
  • 92.23 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 2789.540us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 13.585us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.693us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 722.833us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 359.463us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.693us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.828us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 186.000s 12304.914us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 38.000s 11760.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 29.000s 17941.564us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 116.000s 14953.498us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 129.000s 19401.300us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 5.000s 4008.143us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3854.699us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 15.000s 17109.974us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1618.089us 1 1 100.00
sram_ctrl_partial_access_b2b 155.000s 208996.657us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 704.269us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 676.284us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 2654.333us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2345.724us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 696.119us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 109.000s 423734.324us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 49.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 543.311us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 543.311us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.585us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.693us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.828us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 90.907us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 13.585us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.693us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.828us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 90.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 15411.530us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 289.152us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 289.152us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2345.724us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 2345.724us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.693us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 15.000s 17109.974us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 17109.974us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 17109.974us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3854.699us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 9464.426us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 15411.530us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2110.806us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2789.540us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2789.540us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 15.000s 17109.974us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3854.699us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 2789.540us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1389.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 13229.207us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 82290093857482418351610621978265761637673239943134944030723210833337003069939 86
UVM_INFO @ 704268991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 8515602085687317886435705720960025983502350074208913459341223061825820531213 86
UVM_INFO @ 676284425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 70041074224348427049801634846317147871508428850667502937369808836464364064727 86
UVM_INFO @ 2654333078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---