Simulation Results: sysrst_ctrl

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.42 %
  • code
  • 93.99 %
  • assert
  • 95.21 %
  • func
  • 67.07 %
  • line
  • 97.64 %
  • branch
  • 97.74 %
  • cond
  • 95.08 %
  • toggle
  • 100.00 %
  • FSM
  • 79.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.880s 2111.035us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.660s 2467.450us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.860s 2441.741us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.470s 2333.436us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 6.570s 6035.097us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.410s 2039.082us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 82.930s 75600.452us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.050s 2709.148us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.580s 2160.404us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.410s 2039.082us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.050s 2709.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 82.380s 47101.508us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 26.190s 26339.737us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.810s 2814.590us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.940s 3257.369us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.670s 2528.799us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.450s 2249.792us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.710s 4457.219us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.010s 2612.762us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 5.580s 31891.336us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 63.740s 34370.527us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 156.800s 90653.717us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.000s 2025.487us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.480s 2048.899us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.180s 2106.324us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.180s 2106.324us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.570s 6035.097us 1 1 100.00
sysrst_ctrl_csr_rw 4.410s 2039.082us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.050s 2709.148us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.160s 7043.969us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 6.570s 6035.097us 1 1 100.00
sysrst_ctrl_csr_rw 4.410s 2039.082us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.050s 2709.148us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 13.160s 7043.969us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 2.680s 22550.514us 1 1 100.00
sysrst_ctrl_tl_intg_err 60.680s 42524.319us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 60.680s 42524.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.530s 3364.688us 1 1 100.00