Simulation Results: uart

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.69 %
  • code
  • 92.58 %
  • assert
  • 98.56 %
  • func
  • 50.92 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.02 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.990s 776.120us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 24.944us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.850s 33.108us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.210s 359.329us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.960s 23.459us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.570s 156.088us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.850s 33.108us 1 1 100.00
uart_csr_aliasing 0.960s 23.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 122.550s 211948.880us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.990s 776.120us 1 1 100.00
uart_tx_rx 122.550s 211948.880us 1 1 100.00
parity_error 2 2 100.00
uart_intr 25.640s 41078.110us 1 1 100.00
uart_rx_parity_err 8.220s 38897.129us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 122.550s 211948.880us 1 1 100.00
uart_intr 25.640s 41078.110us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 90.160s 109494.269us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 10.930s 13888.941us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 22.040s 23011.570us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 25.640s 41078.110us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 25.640s 41078.110us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 25.640s 41078.110us 1 1 100.00
perf 1 1 100.00
uart_perf 72.480s 17245.595us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 13.360s 10896.945us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 13.360s 10896.945us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 24.750s 101615.535us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.460s 4587.043us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.900s 1410.629us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 10.700s 7059.812us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 128.600s 239796.195us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 230.360s 844408.867us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.740s 50.448us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.690s 15.058us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.690s 120.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.690s 120.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 24.944us 1 1 100.00
uart_csr_rw 0.850s 33.108us 1 1 100.00
uart_csr_aliasing 0.960s 23.459us 1 1 100.00
uart_same_csr_outstanding 0.730s 28.127us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 24.944us 1 1 100.00
uart_csr_rw 0.850s 33.108us 1 1 100.00
uart_csr_aliasing 0.960s 23.459us 1 1 100.00
uart_same_csr_outstanding 0.730s 28.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.030s 41.524us 1 1 100.00
uart_tl_intg_err 0.940s 141.519us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.940s 141.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.200s 16523.169us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 35279039503327431605662569396750522212834744387412416103432019492182614556842 78
UVM_ERROR @ 50565334794 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 50565374794 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (140 [0x8c] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 50724894794 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 50849654794 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0