Simulation Results: adc_ctrl

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.47 %
  • code
  • 93.85 %
  • assert
  • 92.38 %
  • func
  • 13.17 %
  • line
  • 98.77 %
  • branch
  • 97.28 %
  • cond
  • 86.97 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
57.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.160s 6021.257us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.000s 1088.293us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.220s 430.136us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 14.270s 51396.392us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.050s 1179.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.960s 587.200us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.220s 430.136us 1 1 100.00
adc_ctrl_csr_aliasing 2.050s 1179.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.670s 301.018us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.070s 377.672us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.810s 432.549us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.870s 317.740us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.130s 412.615us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.800s 455.063us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.150s 322.683us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.090s 402.531us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.690s 5171.203us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 11.780s 41239.446us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 166.930s 118557.499us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 21.800s 47993.755us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.880s 389.316us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.710s 465.530us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.590s 599.156us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.590s 599.156us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1088.293us 1 1 100.00
adc_ctrl_csr_rw 1.220s 430.136us 1 1 100.00
adc_ctrl_csr_aliasing 2.050s 1179.059us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.820s 4975.847us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.000s 1088.293us 1 1 100.00
adc_ctrl_csr_rw 1.220s 430.136us 1 1 100.00
adc_ctrl_csr_aliasing 2.050s 1179.059us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.820s 4975.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.260s 4167.302us 1 1 100.00
adc_ctrl_tl_intg_err 2.690s 4387.925us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.690s 4387.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.010s 715.529us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 9 test runs
adc_ctrl_filters_polled 104739007440033207800984042094515438795308613612106557530452110838437023760781 386
UVM_INFO @ 301018467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 18093440609861792419544064197049387535250684916202550040594100163246804509121 386
UVM_INFO @ 377672173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 2821730016907441321809735215723928675966227934277412397746405922235765108363 386
UVM_INFO @ 432548732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 72214311875916392969689034634150868046862389714112096588176263368109936947103 386
UVM_INFO @ 317739645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 56969349206577512031060048304325525521542609620955980373571865415401023489298 386
UVM_INFO @ 412614735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 75851370335345552775273959149003419008075939312599207064896451178373163451498 386
UVM_INFO @ 455063010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 34357886261403559145956152984877287245400962675711074168246506130477417980056 386
UVM_INFO @ 402530565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 44716048945534288727409802647753122083530328942641409410102930263388049116462 386
UVM_INFO @ 322683345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 99669856418010977691785730533588792425853666669318823697925087424116535145231 399
UVM_INFO @ 715529081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---