Simulation Results: aes/masked

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.19 %
  • code
  • 93.43 %
  • assert
  • 98.23 %
  • func
  • 75.91 %
  • block
  • 94.03 %
  • line
  • 95.72 %
  • branch
  • 86.69 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 144.827us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 1922.593us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 112.640us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 89.533us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 851.791us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 157.631us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 65.241us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 89.533us 1 1 100.00
aes_csr_aliasing 2.000s 157.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 1922.593us 1 1 100.00
aes_config_error 3.000s 99.589us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 1922.593us 1 1 100.00
aes_config_error 3.000s 99.589us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_b2b 4.000s 268.141us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 1922.593us 1 1 100.00
aes_config_error 3.000s 99.589us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 65.869us 1 1 100.00
aes_config_error 3.000s 99.589us 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 82.093us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 70.000s 6861.689us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_sideload 4.000s 96.512us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 147.537us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 16.000s 627.524us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 130.373us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 183.148us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 183.148us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.640us 1 1 100.00
aes_csr_rw 1.000s 89.533us 1 1 100.00
aes_csr_aliasing 2.000s 157.631us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.104us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 112.640us 1 1 100.00
aes_csr_rw 1.000s 89.533us 1 1 100.00
aes_csr_aliasing 2.000s 157.631us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 25.619us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 166.746us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 744.797us 1 1 100.00
aes_tl_intg_err 2.000s 588.353us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 588.353us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 1922.593us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
aes_core_fi 1.000s 78.689us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 99.589us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_core_fi 1.000s 78.689us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 83.669us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 174.021us 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 153.508us 1 1 100.00
aes_sideload 4.000s 96.512us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 174.021us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 174.021us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 174.021us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 174.021us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 174.021us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 153.508us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 794.654us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 794.654us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 794.654us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 794.654us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 352.822us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_ctr_fi 2.000s 61.290us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 794.654us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 794.654us 0 1 0.00
aes_control_fi 18.000s 10011.583us 0 1 0.00
aes_cipher_fi 3.000s 134.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 216.371us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 18092527878773970028323597522949929866260339789176598106623911317207821807874 1690
UVM_INFO @ 25619248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 63929680623691418958629879147985604440544244390959049017514115027716429568030 10888
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 91863800604478609637468422667751174626010148334957642555106614414958641136295 139
UVM_INFO @ 10011582633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 79467916025071609272299053368642746689771299376164982035863355300602676584835 158
UVM_INFO @ 216370678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---