Simulation Results: aes/unmasked

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 89.23 %
  • assert
  • 97.73 %
  • func
  • 72.47 %
  • block
  • 89.60 %
  • line
  • 92.13 %
  • branch
  • 80.13 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 67.601us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 71.967us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 50.731us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 75.439us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 2508.138us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 129.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 108.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 75.439us 1 1 100.00
aes_csr_aliasing 2.000s 129.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 71.967us 1 1 100.00
aes_config_error 2.000s 58.591us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 71.967us 1 1 100.00
aes_config_error 2.000s 58.591us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_b2b 5.000s 120.234us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 71.967us 1 1 100.00
aes_config_error 2.000s 58.591us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 123.300us 1 1 100.00
aes_config_error 2.000s 58.591us 1 1 100.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 92.694us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 559.522us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_sideload 2.000s 100.289us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 128.532us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 305.064us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 91.110us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 94.546us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 94.546us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 50.731us 1 1 100.00
aes_csr_rw 1.000s 75.439us 1 1 100.00
aes_csr_aliasing 2.000s 129.119us 1 1 100.00
aes_same_csr_outstanding 2.000s 256.561us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 50.731us 1 1 100.00
aes_csr_rw 1.000s 75.439us 1 1 100.00
aes_csr_aliasing 2.000s 129.119us 1 1 100.00
aes_same_csr_outstanding 2.000s 256.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 178.119us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 158.239us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 3777.504us 1 1 100.00
aes_tl_intg_err 2.000s 241.732us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 241.732us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 71.967us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
aes_core_fi 2.000s 101.349us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 58.591us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_core_fi 2.000s 101.349us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 123.677us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 133.699us 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 73.842us 1 1 100.00
aes_sideload 2.000s 100.289us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 133.699us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 133.699us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 133.699us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 133.699us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 133.699us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 73.842us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.126us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.126us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.126us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 173.126us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1.000s 5.194us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_ctr_fi 2.000s 68.447us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 173.126us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 173.126us 0 1 0.00
aes_control_fi 2.000s 52.103us 1 1 100.00
aes_cipher_fi 23.000s 10004.791us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 11.829us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed 1 test run
aes_alert_reset 97466862203696582161833544149903364809572850259165714664809562791291668372177 325
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 5194143 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 5194143 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 5194143 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 5194143 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 15673494872674375052000011704537830873118856396644618435904185949933284221909 6778
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 37191290012961533201638395926495101361117308481374979035788843594219285990780 154
UVM_INFO @ 10004790782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 50322205699128724800033594870802183603199066451021736633360461934188327159166 135
UVM_INFO @ 11828621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---