Simulation Results: alert_handler

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.15 %
  • code
  • 90.02 %
  • assert
  • 98.12 %
  • func
  • 76.31 %
  • line
  • 99.70 %
  • branch
  • 98.16 %
  • cond
  • 91.54 %
  • toggle
  • 84.88 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.410s 70.944us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.030s 114.714us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 74.590s 1199.542us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 34.540s 2933.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.150s 67.256us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.030s 114.714us 1 1 100.00
alert_handler_csr_aliasing 34.540s 2933.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 126.220s 45450.783us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 28.260s 5382.048us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1006.120s 18052.660us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 13.660s 1516.376us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 8.360s 927.761us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 12.220s 364.766us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 289.000s 11592.463us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1494.830s 164725.038us 1 1 100.00
alert_handler_lpg_stub_clk 1369.220s 79016.901us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 6.080s 444.328us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.380s 263.382us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.970s 23.937us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.060s 13.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.510s 678.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.510s 678.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.410s 70.944us 1 1 100.00
alert_handler_csr_rw 3.030s 114.714us 1 1 100.00
alert_handler_csr_aliasing 34.540s 2933.864us 1 1 100.00
alert_handler_same_csr_outstanding 6.270s 414.278us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.410s 70.944us 1 1 100.00
alert_handler_csr_rw 3.030s 114.714us 1 1 100.00
alert_handler_csr_aliasing 34.540s 2933.864us 1 1 100.00
alert_handler_same_csr_outstanding 6.270s 414.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 167.790s 17263.770us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 167.790s 17263.770us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 167.790s 17263.770us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 167.790s 17263.770us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 335.860s 43247.501us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
alert_handler_tl_intg_err 2.210s 38.030us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.210s 38.030us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 167.790s 17263.770us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 39.100s 1298.266us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.660s 1516.376us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1494.830s 164725.038us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 13.660s 1516.376us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1006.120s 18052.660us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1006.120s 18052.660us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 15.790s 1845.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 29.030s 1404.035us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 95295818083446421753981501643312226729679815145648316930432045658358672146837 153
UVM_INFO @ 11592462721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 83276025718090566637132138399697311110193415995051409594254857948818848176056 160
UVM_INFO @ 263381580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 95068999296775397084925032738230752299585600470650815443047706693012447208413 90
UVM_INFO @ 1404034870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---