Simulation Results

Simulation Results: chip

27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.44 %

code
81.40 %

assert
97.49 %

func
38.42 %

line
94.18 %

branch
93.55 %

cond
88.55 %

toggle
73.58 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.45%
V2S		100.00%
V3		65.38%
unmapped		54.55%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	133.480s	3395.616us	1	1	100.00
	chip_sw_example_rom	92.850s	3433.761us	1	1	100.00
	chip_sw_example_manufacturer	133.540s	3509.504us	1	1	100.00
	chip_sw_example_concurrency	189.060s	3102.662us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	182.500s	5018.163us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	289.070s	4682.571us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2871.290s	42744.371us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4377.730s	31717.197us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	97.260s	2416.802us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4377.730s	31717.197us	1	1	100.00
	chip_csr_rw	289.070s	4682.571us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	9.390s	208.456us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	281.710s	5102.458us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	281.710s	5102.458us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	281.710s	5102.458us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	440.360s	4584.756us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	440.360s	4584.756us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	443.470s	5173.319us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	416.540s	5010.910us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	368.420s	5229.885us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	393.820s	5093.479us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	438.380s	5019.371us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	290.640s	4138.236us	1	1	100.00

209/277 passed

75.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	190.190s	6321.973us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	190.190s	6321.973us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	211.050s	3300.753us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	146.030s	3328.725us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	141.950s	4038.585us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	922.360s	13785.683us	1	1	100.00
	chip_tap_straps_testunlock0	209.910s	4317.138us	1	1	100.00
	chip_tap_straps_rma	274.250s	5072.900us	1	1	100.00
	chip_tap_straps_prod	526.980s	7821.554us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	542.140s	7503.293us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	542.140s	7503.293us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	627.400s	8122.184us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1035.410s	13049.094us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.910s	4865.828us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.630s	5775.981us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4161.990s	19912.186us	1	1	100.00
	chip_sw_aes_enc_jitter_en	206.710s	3479.163us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	768.840s	6520.993us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	177.500s	3320.441us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1482.770s	14155.075us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	235.870s	4282.833us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	455.480s	6741.600us	1	1	100.00
	chip_sw_clkmgr_jitter	175.730s	3409.443us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	191.480s	4041.040us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	447.660s	6172.445us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	273.210s	5604.693us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	205.560s	3487.856us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	273.210s	5604.693us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	236.690s	4225.162us	1	1	100.00
	chip_sw_aes_smoketest	177.300s	2988.051us	1	1	100.00
	chip_sw_aon_timer_smoketest	230.170s	3719.506us	1	1	100.00
	chip_sw_clkmgr_smoketest	193.810s	3992.280us	1	1	100.00
	chip_sw_csrng_smoketest	195.440s	3862.379us	1	1	100.00
	chip_sw_entropy_src_smoketest	823.820s	7220.561us	1	1	100.00
	chip_sw_gpio_smoketest	188.740s	3621.000us	1	1	100.00
	chip_sw_hmac_smoketest	213.380s	3713.392us	1	1	100.00
	chip_sw_kmac_smoketest	187.030s	4146.464us	1	1	100.00
	chip_sw_otbn_smoketest	1276.370s	9063.791us	1	1	100.00
	chip_sw_pwrmgr_smoketest	309.440s	7866.726us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	326.270s	5807.635us	1	1	100.00
	chip_sw_rv_plic_smoketest	217.060s	3702.317us	1	1	100.00
	chip_sw_rv_timer_smoketest	164.450s	3899.773us	1	1	100.00
	chip_sw_rstmgr_smoketest	157.920s	3779.473us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	180.900s	3266.804us	1	1	100.00
	chip_sw_uart_smoketest	184.400s	3608.782us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	157.840s	2567.014us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	452.600s	6769.236us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	8060.860s	60170.262us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3247.410s	15470.685us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	32.149s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1022.890s	14832.017us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	638.360s	15379.847us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7070.370s	53303.052us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7192.970s	57508.133us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	72.020s	2794.954us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	72.020s	2794.954us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4377.730s	31717.197us	1	1	100.00
	chip_same_csr_outstanding	2819.930s	27619.415us	1	1	100.00
	chip_csr_hw_reset	182.500s	5018.163us	1	1	100.00
	chip_csr_rw	289.070s	4682.571us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4377.730s	31717.197us	1	1	100.00
	chip_same_csr_outstanding	2819.930s	27619.415us	1	1	100.00
	chip_csr_hw_reset	182.500s	5018.163us	1	1	100.00
	chip_csr_rw	289.070s	4682.571us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	26.890s	1017.396us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.660s	44.568us	1	1	100.00
	xbar_smoke_large_delays	59.180s	9787.853us	1	1	100.00
	xbar_smoke_slow_rsp	39.990s	4665.532us	1	1	100.00
	xbar_random_zero_delays	35.240s	619.145us	1	1	100.00
	xbar_random_large_delays	202.610s	31262.006us	1	1	100.00
	xbar_random_slow_rsp	262.310s	28234.727us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	18.480s	186.422us	1	1	100.00
	xbar_error_and_unmapped_addr	3.620s	18.859us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	37.720s	1489.571us	1	1	100.00
	xbar_error_and_unmapped_addr	3.620s	18.859us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	25.740s	478.699us	1	1	100.00
	xbar_access_same_device_slow_rsp	353.650s	44092.980us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	14.540s	656.838us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	26.070s	428.207us	1	1	100.00
	xbar_stress_all_with_error	161.220s	6024.054us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	60.820s	2741.103us	1	1	100.00
	xbar_stress_all_with_reset_error	134.980s	2223.646us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3247.410s	15470.685us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	494.600s	7668.415us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	391.660s	5455.390us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	233.163s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	10.361s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	12.453s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	19.556s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	11.517s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	180.746s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	27.764s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	69.359s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.580s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.820s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	139.367s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	99.350s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	68.328s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	38.161s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	56.938s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	23.640s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	21.530s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	24.790s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.860s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	21.050s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.710s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.700s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.400s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.350s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.760s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.130s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.110s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	21.640s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	20.440s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	21.910s	10.140us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	75.908s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	126.570s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	83.012s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	10.320s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	110.981s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	6029.110s	29816.308us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6214.020s	31030.447us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6106.350s	31617.761us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3353.190s	19388.486us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3066.780s	34370.332us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3066.780s	34370.332us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	186.070s	3107.832us	1	1	100.00
	chip_sw_aes_enc_jitter_en	206.710s	3479.163us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	226.820s	3331.767us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	187.470s	3750.967us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1822.050s	12734.081us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	199.410s	3890.787us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	379.790s	6930.595us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	518.260s	6556.011us	1	1	100.00
	chip_plic_all_irqs_10	242.560s	3794.420us	1	1	100.00
	chip_plic_all_irqs_20	371.960s	4567.934us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	216.250s	3784.373us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	987.780s	12870.392us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	289.620s	4355.727us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	178.650s	3727.249us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.161s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	797.800s	7208.890us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	739.140s	6335.293us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	861.040s	8792.197us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9106.500s	257579.401us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	244.740s	4840.617us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	309.440s	7866.726us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	244.740s	4840.617us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	440.730s	8903.631us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	440.730s	8903.631us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	334.960s	7561.084us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	390.010s	6106.409us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	682.200s	6577.587us	1	1	100.00
	chip_sw_aes_idle	187.470s	3750.967us	1	1	100.00
	chip_sw_hmac_enc_idle	193.470s	3588.173us	1	1	100.00
	chip_sw_kmac_idle	170.060s	3585.980us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	297.900s	4661.998us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	380.430s	5022.872us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	283.880s	6204.690us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	431.440s	7461.119us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	786.870s	14066.967us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	387.180s	5103.239us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	375.880s	5310.597us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	432.070s	4671.283us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	438.050s	5136.282us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	415.360s	4135.892us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	377.410s	4496.507us	1	1	100.00
	chip_sw_ast_clk_outputs	627.400s	8122.184us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	412.220s	8667.369us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	432.070s	4671.283us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	438.050s	5136.282us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.910s	4865.828us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.630s	5775.981us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4161.990s	19912.186us	1	1	100.00
	chip_sw_aes_enc_jitter_en	206.710s	3479.163us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	768.840s	6520.993us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	177.500s	3320.441us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1482.770s	14155.075us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	235.870s	4282.833us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	455.480s	6741.600us	1	1	100.00
	chip_sw_clkmgr_jitter	175.730s	3409.443us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	172.760s	3504.162us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	436.680s	5150.147us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	656.490s	7655.218us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4423.090s	25361.808us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	162.200s	3232.637us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	195.880s	3730.771us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1511.270s	15009.644us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	209.600s	4214.356us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	331.500s	5746.459us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1347.500s	24943.912us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	13384.820s	149458.172us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	627.400s	8122.184us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	390.570s	4751.311us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	297.730s	4406.702us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	797.800s	7208.890us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1088.720s	7970.306us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	192.980s	3444.506us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	543.030s	9800.255us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	200.200s	2869.886us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2556.370s	14688.701us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	179.960s	3031.840us	1	1	100.00
	chip_sw_edn_entropy_reqs	588.450s	6897.778us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	179.960s	3031.840us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1088.720s	7970.306us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	150.180s	3717.105us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1296.270s	21479.308us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	552.600s	5805.789us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.630s	5775.981us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	354.460s	4170.848us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.910s	4865.828us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3922.640s	44667.232us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1296.270s	21479.308us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	271.960s	3791.713us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3922.640s	44667.232us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	128.260s	4439.313us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	628.970s	6303.429us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	435.080s	5361.737us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	435.080s	5361.737us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	163.170s	3004.201us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	177.500s	3320.441us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	193.470s	3588.173us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	791.430s	6604.974us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1646.800s	12018.467us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	497.020s	6560.088us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	384.360s	4547.182us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	395.950s	5694.312us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	347.540s	4877.617us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1482.770s	14155.075us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1690.990s	13233.122us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1822.050s	12734.081us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4987.080s	20018.537us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	173.580s	3924.773us	1	1	100.00
	chip_sw_kmac_mode_kmac	203.060s	4427.400us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	235.870s	4282.833us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	158.240s	3221.730us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	894.770s	7364.935us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	170.060s	3585.980us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	379.790s	6930.595us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	922.360s	13785.683us	1	1	100.00
	chip_tap_straps_rma	274.250s	5072.900us	1	1	100.00
	chip_tap_straps_prod	526.980s	7821.554us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	152.870s	2986.599us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1520.760s	13160.688us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	214.740s	3824.595us	0	1	0.00
	chip_sw_flash_rma_unlocked	3922.640s	44667.232us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	240.670s	3913.749us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	507.900s	8302.951us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	529.390s	7643.666us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	662.900s	7609.622us	0	1	0.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	369.030s	10110.706us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	660.080s	12371.253us	1	1	100.00
	chip_prim_tl_access	128.260s	4439.313us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	412.220s	8667.369us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	387.180s	5103.239us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	375.880s	5310.597us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	432.070s	4671.283us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	438.050s	5136.282us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	415.360s	4135.892us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	377.410s	4496.507us	1	1	100.00
	chip_tap_straps_dev	922.360s	13785.683us	1	1	100.00
	chip_tap_straps_rma	274.250s	5072.900us	1	1	100.00
	chip_tap_straps_prod	526.980s	7821.554us	1	1	100.00
	chip_rv_dm_lc_disabled	747.000s	19147.793us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	237.280s	4713.132us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	131.980s	3707.279us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	113.160s	3810.940us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	108.170s	3415.970us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	2083.110s	52824.155us	0	1	0.00
	chip_rv_dm_lc_disabled	747.000s	19147.793us	1	1	100.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	687.590s	11211.609us	0	1	0.00
	chip_sw_lc_walkthrough_prod	801.440s	12829.648us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	644.540s	12793.623us	1	1	100.00
	chip_sw_lc_walkthrough_rma	373.730s	7803.908us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2083.110s	52824.155us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	97.440s	2833.321us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	67.280s	2093.093us	1	1	100.00
	rom_volatile_raw_unlock	126.913s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3962.540s	17547.131us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4161.990s	19912.186us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	682.200s	6577.587us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	682.200s	6577.587us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	682.200s	6577.587us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	296.660s	4492.428us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1296.270s	21479.308us	1	1	100.00
	chip_sw_otbn_mem_scramble	296.660s	4492.428us	1	1	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	452.490s	6940.170us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	231.430s	4156.639us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1296.270s	21479.308us	1	1	100.00
	chip_sw_otbn_mem_scramble	296.660s	4492.428us	1	1	100.00
	chip_sw_keymgr_key_derivation	1727.400s	14877.894us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	452.490s	6940.170us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	231.430s	4156.639us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	414.370s	6799.015us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	152.870s	2986.599us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	240.670s	3913.749us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	507.900s	8302.951us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	529.390s	7643.666us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	662.900s	7609.622us	0	1	0.00
	chip_sw_lc_ctrl_transition	733.680s	14226.464us	1	1	100.00
	chip_prim_tl_access	128.260s	4439.313us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	128.260s	4439.313us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	810.440s	7927.075us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	92.310s	3496.984us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	975.160s	28623.005us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	291.180s	7843.169us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	298.720s	7624.856us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	436.320s	8573.908us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	749.840s	21386.608us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	234.210s	6853.240us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	440.730s	8903.631us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	974.070s	13637.401us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	431.840s	6628.178us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	92.310s	3496.984us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	316.050s	6681.870us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	2149.930s	35288.196us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	319.030s	6966.849us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	180.370s	4181.764us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	654.320s	13200.358us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	686.440s	9549.646us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	991.760s	15926.854us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2100.870s	29701.275us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	179.270s	3995.302us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	369.030s	10110.706us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	369.030s	10110.706us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	991.760s	15926.854us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	654.320s	13200.358us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	431.840s	6628.178us	1	1	100.00
	chip_sw_pwrmgr_smoketest	309.440s	7866.726us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	295.820s	4147.113us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	429.820s	7546.355us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	273.730s	4714.862us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	987.780s	12870.392us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	191.730s	3311.166us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	739.140s	6335.293us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	518.660s	5522.352us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	497.140s	5833.183us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	224.900s	4221.478us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	231.430s	4156.639us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	429.820s	7546.355us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	429.820s	7546.355us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	172.710s	3469.108us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	507.790s	8207.026us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	952.450s	14022.011us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	295.820s	4147.113us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	225.490s	4410.267us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1341.610s	14124.512us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	274.250s	5072.900us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	747.000s	19147.793us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	518.260s	6556.011us	1	1	100.00
	chip_plic_all_irqs_10	242.560s	3794.420us	1	1	100.00
	chip_plic_all_irqs_20	371.960s	4567.934us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	171.100s	3811.406us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	200.680s	4115.333us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3247.410s	15470.685us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	419.060s	6458.337us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	236.900s	3623.627us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	262.220s	4124.483us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	215.180s	4324.924us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	452.490s	6940.170us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	455.480s	6741.600us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	543.680s	8463.694us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	604.270s	11676.810us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	660.080s	12371.253us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
	chip_sw_data_integrity_escalation	542.140s	7503.293us	1	1	100.00
chip_sw_sysrst_ctrl_reset				1	2	50.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	686.440s	9549.646us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	851.480s	23197.624us	0	1	0.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	214.200s	3978.894us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	259.540s	4177.800us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	330.750s	5353.673us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				0	1	0.00
	chip_sw_sysrst_ctrl_reset	851.480s	23197.624us	0	1	0.00
chip_sw_sysrst_ctrl_sleep_reset				0	1	0.00
	chip_sw_sysrst_ctrl_reset	851.480s	23197.624us	0	1	0.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2236.360s	21088.339us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2236.360s	21088.339us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	310.930s	7899.442us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3066.780s	34370.332us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	191.180s	3439.264us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	127.700s	3252.230us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	319.210s	4333.961us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	299.040s	4049.118us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	969.150s	8647.351us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5630.880s	32494.678us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2018.090s	13023.045us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	190.430s	4072.051us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	170.120s	2544.737us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	184.180s	3630.428us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9902.710s	69014.853us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1143.670s	7222.113us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	255.630s	4713.711us	0	1	0.00
	rom_e2e_jtag_debug_dev	500.530s	6084.825us	0	1	0.00
	rom_e2e_jtag_debug_rma	219.260s	3921.971us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	94.460s	2500.765us	0	1	0.00
	rom_e2e_jtag_inject_dev	80.500s	2897.350us	0	1	0.00
	rom_e2e_jtag_inject_rma	81.280s	3257.888us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	46.222s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	318.070s	4408.921us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	347.660s	3912.024us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	530.720s	4635.349us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1541.850s	11070.999us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	256.350s	2478.943us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	656.490s	5800.721us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	89.590s	2346.388us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	257.120s	4246.627us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	423.590s	7177.539us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	364.600s	5856.767us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	991.760s	15926.854us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	255.630s	4713.711us	0	1	0.00
	rom_e2e_jtag_debug_dev	500.530s	6084.825us	0	1	0.00
	rom_e2e_jtag_debug_rma	219.260s	3921.971us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	396.680s	6440.449us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	392.590s	5822.810us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5761.400s	38090.423us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5761.400s	38090.423us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	194.110s	4031.505us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	440.360s	4584.756us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3103.030s	18933.495us	1	1	100.00

unmapped

6/11 passed

54.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				6	11	54.55
	chip_sival_flash_info_access	195.760s	3615.316us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	21.400s	10.120us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	7.070s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	153.270s	3868.122us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	224.160s	3276.306us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	219.550s	3936.866us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.771s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	213.870s	2972.775us	1	1	100.00
	ate_bootstrap_flash_erase	598.600s	10010.200us	0	1	0.00
	ate_bootstrap_one_frame	6456.760s	44045.455us	1	1	100.00
	ate_bootstrap_disjoint	9221.320s	79377.210us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	10634568591015013138416890805867976433790626973213984950639460941691686913169	None	---- STDERR ---- Another command (pid=2081571) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	66467402299890732552981426261593577805349404292964876663424029550347140784575	None	Another command (pid=832586) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=834381) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=811348) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	57774610323299263277010597043020355528323387773155426718622496943195958853444	None	Another command (pid=634278) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=648650) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=641515) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	99844969926805786960856891287015659445118026593096818258029641723786951625711	None	Another command (pid=660401) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=616268) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=673500) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12008175751447779581213554195440488424049565380469206393360780337520926849521	None	Another command (pid=692475) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=693645) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=697607) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	79051328777264138194674475445284973923419083317894954712973830623126482426018	None	Another command (pid=680678) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=671039) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=676744) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	90650567930804269368221111568210489049161644921305625706188229540792184741918	None	Another command (pid=693645) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=697607) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=698676) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	38184069154094354708397271598961034749060520574179387174368853431938800856285	None	Another command (pid=621023) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=630280) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=652879) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	2640504988261620487675717352479138157293378231204141462998252134309719859255	None	Another command (pid=752820) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=766058) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=761571) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27005388972109812759036220384127165403445481969438144177338609704793192081264	None	Another command (pid=644137) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=551623) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=621023) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	107353719905104115748262685910463113514170295474697514205969101226422675471597	None	Another command (pid=652879) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=611495) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=646466) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	68457470036867526558844078802390723135829993602518426076095593787785183418412	None	Another command (pid=490115) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=422819) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=490428) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	23245391789792705849413724315469190413682722628302925008882225790039393154793	None	Another command (pid=630280) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=652879) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=611495) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	91329113738025396275987784647156244303699268186599749242788250088037602417505	None	Another command (pid=611495) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=646466) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=634278) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	45589202023439518052547114524123132035780248673145261423577885370343322425961	None	Another command (pid=506117) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=627325) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=635207) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	71735113118513010669530858457285277325759391533728241367383989680619764643714	None	Another command (pid=710911) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=711402) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=712187) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	6545677135871507674396947504317763580000251995873005919234248779998422248914	None	Another command (pid=382873) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=417926) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=390909) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	30602034653656515776407306552588751577743375763532270424559147657800543954865	None	Another command (pid=687078) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=670240) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=688345) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	90546077702600465949489212176894923622417050353919151975814908832470270995450	None	Another command (pid=489529) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=581324) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=486591) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	35476585286411856182289447652708818683663843649096847284809483918512306504563	None	Another command (pid=382873) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=417926) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=390909) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	79651146407141199797831995107810334719091289463336066271779475326507574078016	None	Another command (pid=680678) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=671039) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=676744) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	68933612354146523335664248357655658324950209193244761408074893920223857023715	None	Another command (pid=591089) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=596013) is running. Waiting for it to complete on the server (server_pid=288406)... Another command (pid=599807) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	29999442616747160641860432857217532241572348788352130803112248258716057868624	None	---- STDERR ---- Another command (pid=379687) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	4742364935362533125993310882529708033855308417082274768941984766464317442367	None	---- STDERR ---- Another command (pid=379687) is running. Waiting for it to complete on the server (server_pid=288406)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(rstreqs[*] && (reset_cause == HwReq))'				6 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	102977514558049233618103320272106372387270836688103918930452694626578404493369	344	UVM_ERROR @ 13200.357500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13200.357500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	82444625253940094630971948644493391587566414508342034961312699566084569677373	314	UVM_ERROR @ 6853.240000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6853.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	20216068249207473243387606798019703259666004239545529406869704954911715314152	325	UVM_ERROR @ 7624.856000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7624.856000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16112693885631182949911096713731043196602847593717818614121721735227151907731	416	UVM_ERROR @ 35288.195500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 35288.195500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sysrst_ctrl_reset	73791812088609671251147564104063272136868222827357282778730846440387484680784	334	UVM_ERROR @ 23197.624000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 23197.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	28024923099574982341492361948106476664376977702762092148637478030307038914528	319	UVM_ERROR @ 8903.631000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8903.631000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	38200580889832710520098179389955536266194577776003854233029154459080787740659	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	66165267280028894336746378310525591140176900121003360657175415253727376359172	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	5263087368915826880030715621778015248198454257199392928560474582589254497905	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	52517672731710648789733208919819643897551368986471955188348364874765771946274	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	106382772473719909291129872905631631612718991220511511368954096996773338765237	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	19858572159662417946466566006937526621633539935684118920450106389860935772298	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	23437671363664002961105366393765218671097588889525163685206262695552204412281	366	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	3319660356438638053160902635347286952772451337614761580756653663719276547682	365	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	58711711443894743270021359814551422016974582872448297921491292999981516236062	363	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	43004310041107606562252790261011975306776562887400246445504789235742770483765	326	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	10669378290718732961623380352685961766525211349029641716981755885324491207220	325	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	82857361465272841692686874406302912118249739567670055031650540881178226666978	327	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	106696017734963834185984874982962416467046354023712096067269476167839583704964	369	UVM_INFO @ 11211.608984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	14611673984355247428734901203954179231185287684905565022874711833788807983052	369	UVM_INFO @ 12829.647636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	96604959849821926359344712780191886141763934974000383978276548492873871412946	341	UVM_INFO @ 7803.908266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	31706307324232470388411118367313390496034265348752183598171531926612851267182	327	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	95289349744964047052487668362693018929536200513607779101316827641465357446539	327	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	16542999994567845153373299090427664665182634562862233981990887778804645131254	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				2 test runs
	chip_sw_otp_ctrl_escalation	55681475934843985211758374461959195872133065024742503675804535019484171457897	316	UVM_ERROR @ 4246.627224 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 4246.627224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	4611570004676675810832557990030880470289816863802095178067149034506704000038	312	UVM_ERROR @ 3444.505576 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3444.505576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	86896553337567874503660808971637856971770004681279800696372703680444478992399	339	UVM_INFO @ 12018.467481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	57667881548438158840429287051639436321875257480060315853986146088486993051059	336	UVM_INFO @ 20018.537213 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	71959211904491540083251719647273207295053206520793171333202698274023990435936	217	TL item was: req: (cip_tl_seq_item@30789) { a_addr: 'h10588 a_data: 'hd87c899b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1b69d d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2794.954410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	18794686397653717615206872622603339430180013545898489733764901242928735170506	224	TL item was: req: (cip_tl_seq_item@30333) { a_addr: 'h10584 a_data: 'h94496fe5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h1aeb0 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2416.802164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	34811948554964376246918067769379395007829952433964885356104922079489939792059	363	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	9185246118359253483730929419321464624152054832970234108040475472901347046631	325	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	28385838553703192882997910533371781076182670719334485829109939902084449030531	365	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	101464660336143531721317358174167572545796018830361611608685527381993716203659	328	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	13164840367854836896669390616283946398729194923485410417610866370295799239481	301	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	16191595573153467617944000715710192163571480777094325258892202266293996746376	329	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	8675182965871543821430533134167562403096722222616382131852217320226971632956	309	UVM_INFO @ 3824.594731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	100115944625636289633875817608411760717042198451686937300335147472164360363936	342	UVM_INFO @ 7609.621860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	91342503725399719244794793776057945157235559469512837137345167793585468293503	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_testunlocks	47435627856710939208741487838589541674509564406534600995994202660711427187068	419	UVM_INFO @ 52824.155442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	28261889196704033608706956552548698617928813380732466282530783602388503348786	303	UVM_ERROR @ 3496.984490 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 3496.984490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	114835597073294655420420040653789158470100555904811040152342671544841653398263	313	UVM_ERROR @ 4181.763825 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 4181.763825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	23000162431745210443755488025867896037188233011454101208407203678277522322958	332	UVM_INFO @ 34370.332016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	44929358655006562157975082278764637196693601438185123194085141475631939118207	307	UVM_INFO @ 3890.786624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	9967603387882030202636211637731047138314408145219080759223701159200398410058	308	UVM_INFO @ 3727.248602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	24225398128846644970109060008178117386439779759480888821936645635031882750070	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	14873485351966034420690904314940375573847334203012370034168395462936635461824	343	UVM_INFO @ 4408.921231 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()				1 test run
	chip_sw_pwrmgr_lowpower_cancel	114397606199569389466024508256062126659760900839389212728396690425452963670042	311	UVM_INFO @ 3936.866212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	62765111148145767414586428990289684052604882262179977576168593478682607576988	329	UVM_INFO @ 14124.511593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	47042154825747575802341425486746776423864385585674873014082744716985679945981	318	UVM_INFO @ 14832.017072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	30508051029477010252220200228677724570235841810307224182947034012069773339775	337	UVM_INFO @ 15379.847155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	9491124610759928656595180850090967729706311730178491540324939722828728343558	327	UVM_INFO @ 13049.093896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	92904414687955185848095638124025936629972336913000081390875352944735055138360	272	UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	82002442340854127544550735734465616345268169324337898856934809295663094711555	319	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5455.389969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	85851793508975114883491887517329258297037555226129396721541575383547268041962	312	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 7668.414505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	40415963838725278332121580536343499047728835378678956644812502997470103465266	325	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	73898660605394166182261183515623629423855491730134729598625018130104039641182	328	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_jtag_debug_test_unlocked0	31716023103622651153653151139913449635313620981127194397404112929915813549555	331	UVM_ERROR @ 4713.710980 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 4713.710980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	1221431257081516288859763483093311008776715532287079996496650795319423492381	327	UVM_ERROR @ 6769.236004 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 6769.236004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---