Simulation Results: clkmgr

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.64 %
  • code
  • 98.37 %
  • assert
  • 95.76 %
  • func
  • 86.79 %
  • line
  • 99.02 %
  • branch
  • 98.64 %
  • cond
  • 95.02 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.780s 25.506us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.720s 19.424us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.650s 152.977us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.140s 70.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.190s 67.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
clkmgr_csr_aliasing 1.140s 70.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.890s 27.621us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.840s 47.746us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.040s 96.465us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.860s 56.463us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.780s 25.506us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.430s 1769.093us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.650s 501.407us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.430s 1769.093us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 26.580s 6771.240us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.780s 35.700us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.380s 121.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.380s 121.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 19.424us 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
clkmgr_csr_aliasing 1.140s 70.408us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 47.961us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.720s 19.424us 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
clkmgr_csr_aliasing 1.140s 70.408us 1 1 100.00
clkmgr_same_csr_outstanding 1.050s 47.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.640s 1.880us 0 1 0.00
clkmgr_tl_intg_err 2.230s 121.861us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.290s 899.040us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.290s 899.040us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.290s 899.040us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.290s 899.040us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.530s 177.406us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.230s 121.861us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.430s 1769.093us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.650s 501.407us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.290s 899.040us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.790s 33.416us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.030s 129.399us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.750s 16.934us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.160s 84.435us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.240s 230.004us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.640s 1.880us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.880s 35.367us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.640s 1.880us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.910s 1165.359us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 72.910s 12632.269us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 89754323888772920577938096153910321768092129630277718434255453732754416277817 77
UVM_INFO @ 1880415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---