Simulation Results: csrng

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.88 %
  • code
  • 92.12 %
  • assert
  • 94.10 %
  • func
  • 65.42 %
  • block
  • 96.75 %
  • line
  • 97.55 %
  • branch
  • 91.93 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 74.163us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 160.974us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 82.160us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 4.000s 82.480us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 83.770us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 25.813us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 82.160us 1 1 100.00
csrng_csr_aliasing 4.000s 83.770us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
alerts 1 1 100.00
csrng_alert 4.000s 174.401us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 116.000s 12240.517us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 116.000s 12240.517us 1 1 100.00
stress_all 0 1 0.00
csrng_stress_all 397.000s 21818.778us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 56.981us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 22.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 88.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 88.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 160.974us 1 1 100.00
csrng_csr_rw 2.000s 82.160us 1 1 100.00
csrng_csr_aliasing 4.000s 83.770us 1 1 100.00
csrng_same_csr_outstanding 3.000s 22.348us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 160.974us 1 1 100.00
csrng_csr_rw 2.000s 82.160us 1 1 100.00
csrng_csr_aliasing 4.000s 83.770us 1 1 100.00
csrng_same_csr_outstanding 3.000s 22.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
csrng_tl_intg_err 3.000s 62.247us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 18.975us 0 1 0.00
csrng_csr_rw 2.000s 82.160us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 4.000s 174.401us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 397.000s 21818.778us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 4.000s 174.401us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 397.000s 21818.778us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 4.000s 174.401us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 62.247us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
csrng_sec_cm 2.000s 78.639us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 317.304us 1 1 100.00
csrng_err 2.000s 23.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.060s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 71370310519033885059990737099755064898668683372480995817849940033741682653471 132
UVM_INFO @ 21818777545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 27910890386903556738736187348553684247227254582268810379109962783821120760787 99
UVM_INFO @ 18974533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 94424337975075347338625832519764536617140617787151662201103778420417834337390 None