Simulation Results: edn/edn0

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 84.87 %
  • assert
  • 98.26 %
  • func
  • 79.17 %
  • line
  • 98.04 %
  • branch
  • 93.86 %
  • cond
  • 88.91 %
  • toggle
  • 90.87 %
  • FSM
  • 52.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 55.529us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 200.616us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 18.272us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.870s 316.203us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.130s 46.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 142.860us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 18.272us 1 1 100.00
edn_csr_aliasing 1.130s 46.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.010s 54.358us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.010s 54.358us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.010s 54.358us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.760s 43.797us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.420s 44.121us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 21.993us 1 1 100.00
disable 2 2 100.00
edn_disable 1.050s 13.238us 1 1 100.00
edn_disable_auto_req_mode 0.980s 31.343us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.430s 66.549us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 41.492us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 42.238us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.050s 128.082us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.050s 128.082us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 200.616us 1 1 100.00
edn_csr_rw 0.760s 18.272us 1 1 100.00
edn_csr_aliasing 1.130s 46.625us 1 1 100.00
edn_same_csr_outstanding 0.800s 58.290us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 200.616us 1 1 100.00
edn_csr_rw 0.760s 18.272us 1 1 100.00
edn_csr_aliasing 1.130s 46.625us 1 1 100.00
edn_same_csr_outstanding 0.800s 58.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
edn_tl_intg_err 1.370s 100.643us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 26.458us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.420s 44.121us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.420s 44.121us 1 1 100.00
edn_sec_cm 5.790s 482.889us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.420s 44.121us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.370s 100.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 55.710s 3082.923us 1 1 100.00