Simulation Results: edn/edn1

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.41 %
  • code
  • 83.05 %
  • assert
  • 97.66 %
  • func
  • 81.51 %
  • line
  • 98.33 %
  • branch
  • 93.51 %
  • cond
  • 89.00 %
  • toggle
  • 87.80 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.110s 18.815us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 18.097us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 13.416us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.640s 286.788us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.960s 49.621us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.930s 25.455us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 13.416us 1 1 100.00
edn_csr_aliasing 0.960s 49.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 31.530us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 31.530us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 31.530us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 20.487us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 75.339us 1 1 100.00
errs 1 1 100.00
edn_err 0.940s 64.092us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 14.084us 1 1 100.00
edn_disable_auto_req_mode 0.920s 42.231us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.100s 472.438us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 53.902us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 264.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.440s 533.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.440s 533.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 18.097us 1 1 100.00
edn_csr_rw 0.770s 13.416us 1 1 100.00
edn_csr_aliasing 0.960s 49.621us 1 1 100.00
edn_same_csr_outstanding 1.070s 34.268us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 18.097us 1 1 100.00
edn_csr_rw 0.770s 13.416us 1 1 100.00
edn_csr_aliasing 0.960s 49.621us 1 1 100.00
edn_same_csr_outstanding 1.070s 34.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
edn_tl_intg_err 1.980s 375.368us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 52.696us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 75.339us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 75.339us 1 1 100.00
edn_sec_cm 2.560s 346.672us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 75.339us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.980s 375.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 32.700s 6551.323us 1 1 100.00