Simulation Results: entropy_src/rng_4bits

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.53 %
  • code
  • 88.52 %
  • assert
  • 83.91 %
  • func
  • 54.15 %
  • block
  • 94.47 %
  • line
  • 97.14 %
  • branch
  • 86.69 %
  • toggle
  • 76.51 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 81.491us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 40.791us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 45.237us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 5.000s 454.041us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 1155.662us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 9.493us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 45.237us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1155.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 81.491us 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
entropy_src_fw_ov 49.000s 13289.111us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 49.000s 13289.111us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 200.000s 13091.720us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
entropy_src_intr 3.000s 66.640us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
entropy_src_functional_alerts 4.000s 659.470us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 51.000s 14369.182us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 252.311us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 48.718us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 16.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 1054.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 1054.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 40.791us 1 1 100.00
entropy_src_csr_rw 1.000s 45.237us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1155.662us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 79.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 40.791us 1 1 100.00
entropy_src_csr_rw 1.000s 45.237us 1 1 100.00
entropy_src_csr_aliasing 3.000s 1155.662us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 79.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 61.066us 1 1 100.00
entropy_src_tl_intg_err 3.000s 168.921us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
entropy_src_cfg_regwen 1.000s 68.892us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
entropy_src_fw_ov 49.000s 13289.111us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
entropy_src_sec_cm 2.000s 61.066us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
entropy_src_sec_cm 2.000s 61.066us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 188.000s 13045.080us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
entropy_src_sec_cm 2.000s 61.066us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
entropy_src_sec_cm 2.000s 61.066us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 168.627us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 659.470us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 168.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 61.000s 14293.834us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 830.522us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 4133870828877486643577944861834916555170065816976830123036349668934404500045 217
UVM_INFO @ 830522305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 77918690090798181033624933247457162857894408328410434521239699611780530989888 113
UVM_INFO @ 9492782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---