Simulation Results: flash_ctrl

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.35 %
  • code
  • 93.74 %
  • assert
  • 96.94 %
  • func
  • 95.36 %
  • line
  • 95.90 %
  • branch
  • 97.08 %
  • cond
  • 93.58 %
  • toggle
  • 95.76 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 56.530s 73.633us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.800s 29.152us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 22.660s 50.870us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 70.640s 16924.242us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 40.830s 3262.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.720s 469.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
flash_ctrl_csr_aliasing 40.830s 3262.192us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.320s 55.370us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.300s 33.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.670s 349.618us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 28.290s 174.304us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1350.410s 143410.898us 1 1 100.00
flash_ctrl_hw_rma_reset 600.420s 160202.238us 1 1 100.00
flash_ctrl_lcmgr_intg 6.390s 72.187us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1178.300s 336108.554us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 243.740s 3366.111us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 100.220s 2318.425us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2058.300s 693405.618us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 88.810s 2833.709us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.760s 134.748us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.430s 47.649us 1 1 100.00
flash_ctrl_re_evict 21.180s 82.161us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 93.820s 60.441us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 93.820s 60.441us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 303.950s 30928.839us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 18.450s 376.308us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 105.330s 69.470us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 399.790s 4597.430us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 393.790s 7218.362us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 918.180s 893.399us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.060s 97.908us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 149.730s 1960.449us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.710s 31.642us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 9.300s 20.890us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 138.790s 88.851us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 69.230s 1801.722us 1 1 100.00
flash_ctrl_otp_reset 64.480s 151.169us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1350.410s 143410.898us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 68.400s 869.564us 1 1 100.00
flash_ctrl_intr_wr 51.150s 9708.481us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 87.390s 23429.472us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 122.040s 94191.841us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 50.340s 2034.787us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 44.580s 979.174us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 15.210s 31.867us 1 1 100.00
flash_ctrl_ro_derr 96.770s 1103.303us 1 1 100.00
flash_ctrl_rw_derr 142.680s 6573.762us 1 1 100.00
flash_ctrl_derr_detect 101.660s 2834.501us 1 1 100.00
flash_ctrl_integrity 380.130s 19722.727us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.950s 29.923us 1 1 100.00
flash_ctrl_ro_serr 100.090s 9928.284us 1 1 100.00
flash_ctrl_rw_serr 140.210s 2100.137us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 49.240s 1117.008us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 55.170s 2815.517us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 109.120s 9848.310us 1 1 100.00
flash_ctrl_write_word_sweep 7.340s 89.219us 1 1 100.00
flash_ctrl_read_word_sweep 8.450s 46.170us 1 1 100.00
flash_ctrl_ro 91.870s 945.455us 1 1 100.00
flash_ctrl_rw 359.990s 20310.079us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 19.650s 690.474us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 616.050s 103260.561us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 28.590s 10060.906us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.360s 38.172us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.430s 17.407us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.770s 239.830us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.770s 239.830us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.660s 50.870us 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
flash_ctrl_csr_aliasing 40.830s 3262.192us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.930s 883.570us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.660s 50.870us 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
flash_ctrl_csr_aliasing 40.830s 3262.192us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.930s 883.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 51.450s 1230.638us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
flash_ctrl_tl_intg_err 209.080s 528.196us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 209.080s 528.196us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 209.080s 528.196us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.680s 276.714us 1 1 100.00
flash_ctrl_wr_intg 7.120s 320.673us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 56.530s 73.633us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 64.480s 151.169us 1 1 100.00
flash_ctrl_disable 10.710s 31.642us 1 1 100.00
flash_ctrl_sec_info_access 39.070s 2405.717us 1 1 100.00
flash_ctrl_connect 9.300s 20.890us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.310s 23.331us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.680s 28.625us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.510s 126.365us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.710s 31.642us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.680s 276.714us 1 1 100.00
flash_ctrl_access_after_disable 6.300s 23.197us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 18.350s 79.748us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.710s 31.642us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 18.450s 376.308us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 359.990s 20310.079us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 140.210s 2100.137us 1 1 100.00
flash_ctrl_rw_derr 142.680s 6573.762us 1 1 100.00
flash_ctrl_integrity 380.130s 19722.727us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1350.410s 143410.898us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.270s 727.995us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.650s 77.934us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 10.120s 23.006us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.080s 946.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.260s 212.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 300.630s 1584.654us 1 1 100.00