Simulation Results: hmac

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.43 %
  • code
  • 97.65 %
  • assert
  • 97.16 %
  • func
  • 43.48 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.240s 194.114us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.920s 35.944us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.010s 33.762us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.660s 5938.650us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.780s 423.054us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.850s 51.684us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.010s 33.762us 1 1 100.00
hmac_csr_aliasing 3.780s 423.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 21.550s 13792.609us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.100s 6009.024us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.910s 238.944us 1 1 100.00
hmac_test_sha384_vectors 21.370s 673.333us 1 1 100.00
hmac_test_sha512_vectors 388.530s 16489.617us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 360.919us 1 1 100.00
hmac_test_hmac384_vectors 9.030s 402.027us 1 1 100.00
hmac_test_hmac512_vectors 10.290s 1558.909us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.220s 1681.272us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 203.220s 8655.203us 1 1 100.00
error 1 1 100.00
hmac_error 13.210s 862.731us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 62.010s 35377.798us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.240s 194.114us 1 1 100.00
hmac_long_msg 21.550s 13792.609us 1 1 100.00
hmac_back_pressure 47.100s 6009.024us 1 1 100.00
hmac_datapath_stress 203.220s 8655.203us 1 1 100.00
hmac_burst_wr 12.220s 1681.272us 1 1 100.00
hmac_stress_all 202.950s 29308.660us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.240s 194.114us 1 1 100.00
hmac_long_msg 21.550s 13792.609us 1 1 100.00
hmac_back_pressure 47.100s 6009.024us 1 1 100.00
hmac_datapath_stress 203.220s 8655.203us 1 1 100.00
hmac_wipe_secret 62.010s 35377.798us 1 1 100.00
hmac_test_sha256_vectors 8.910s 238.944us 1 1 100.00
hmac_test_sha384_vectors 21.370s 673.333us 1 1 100.00
hmac_test_sha512_vectors 388.530s 16489.617us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 360.919us 1 1 100.00
hmac_test_hmac384_vectors 9.030s 402.027us 1 1 100.00
hmac_test_hmac512_vectors 10.290s 1558.909us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.240s 194.114us 1 1 100.00
hmac_long_msg 21.550s 13792.609us 1 1 100.00
hmac_back_pressure 47.100s 6009.024us 1 1 100.00
hmac_datapath_stress 203.220s 8655.203us 1 1 100.00
hmac_burst_wr 12.220s 1681.272us 1 1 100.00
hmac_error 13.210s 862.731us 1 1 100.00
hmac_wipe_secret 62.010s 35377.798us 1 1 100.00
hmac_test_sha256_vectors 8.910s 238.944us 1 1 100.00
hmac_test_sha384_vectors 21.370s 673.333us 1 1 100.00
hmac_test_sha512_vectors 388.530s 16489.617us 1 1 100.00
hmac_test_hmac256_vectors 9.000s 360.919us 1 1 100.00
hmac_test_hmac384_vectors 9.030s 402.027us 1 1 100.00
hmac_test_hmac512_vectors 10.290s 1558.909us 1 1 100.00
hmac_stress_all 202.950s 29308.660us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 202.950s 29308.660us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.720s 15.795us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.740s 19.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.500s 319.510us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.500s 319.510us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.920s 35.944us 1 1 100.00
hmac_csr_rw 1.010s 33.762us 1 1 100.00
hmac_csr_aliasing 3.780s 423.054us 1 1 100.00
hmac_same_csr_outstanding 1.060s 43.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.920s 35.944us 1 1 100.00
hmac_csr_rw 1.010s 33.762us 1 1 100.00
hmac_csr_aliasing 3.780s 423.054us 1 1 100.00
hmac_same_csr_outstanding 1.060s 43.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.160s 93.736us 1 1 100.00
hmac_tl_intg_err 3.630s 1966.961us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.630s 1966.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.240s 194.114us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.310s 214.180us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 90.560s 14378.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.220s 85.417us 1 1 100.00