Simulation Results

Simulation Results: i2c

27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.11 %

code
81.81 %

assert
97.04 %

func
79.49 %

line
96.51 %

branch
92.55 %

cond
85.87 %

toggle
89.47 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	44.190s	14005.567us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	4545.879us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.750s	19.556us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.690s	23.286us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.380s	162.869us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.470s	41.322us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.840s	23.960us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.690s	23.286us	1	1	100.00
	i2c_csr_aliasing	1.470s	41.322us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.360s	808.219us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	199.850s	22022.814us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	190.230s	23862.971us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.690s	20.652us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	163.290s	18492.378us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	34.110s	6593.050us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.850s	176.181us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.290s	1146.651us	1	1	100.00
	i2c_host_fifo_reset_rx	3.150s	1031.324us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	68.800s	4651.778us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	19.060s	633.055us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.190s	42.041us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.020s	486.280us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	54.870s	20189.911us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.950s	4186.888us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.490s	5389.688us	1	1	100.00
	i2c_target_intr_smoke	4.580s	1469.705us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.340s	152.758us	1	1	100.00
	i2c_target_fifo_reset_tx	1.090s	287.903us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	331.520s	59551.526us	1	1	100.00
	i2c_target_stress_rd	17.490s	5389.688us	1	1	100.00
	i2c_target_intr_stress_wr	24.730s	13952.154us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.700s	2240.969us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	15.410s	6499.505us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.870s	889.987us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	17.910s	10013.613us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.930s	2994.855us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.400s	158.861us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	190.230s	23862.971us	1	1	100.00
	i2c_host_perf_precise	5.440s	908.417us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	19.060s	633.055us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.510s	163.840us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.810s	547.271us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.710s	1212.543us	1	1	100.00
	i2c_target_nack_txstretch	1.300s	1329.699us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	10.170s	512.220us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.920s	3071.833us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.800s	19.602us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.810s	50.589us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.940s	145.064us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.940s	145.064us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	19.556us	1	1	100.00
	i2c_csr_rw	0.690s	23.286us	1	1	100.00
	i2c_csr_aliasing	1.470s	41.322us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	39.441us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.750s	19.556us	1	1	100.00
	i2c_csr_rw	0.690s	23.286us	1	1	100.00
	i2c_csr_aliasing	1.470s	41.322us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	39.441us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.250s	80.044us	1	1	100.00
	i2c_sec_cm	1.010s	127.009us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.250s	80.044us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	33.140s	1987.830us	1
target_error_intr				1
	i2c_target_unexp_stop	1.280s	61.642us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.200s	1069.686us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	29209166530005365043202484598865835573891493767929822205244374428641392491901	96	UVM_INFO @ 1987829984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	66233594127034468482380515990637197318966809764556805574794652493077922505165	83	UVM_INFO @ 1069685963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_stress_all	109508511165971815015688024774994794984273338154286366046163055044187997503145	123	UVM_INFO @ 22022814011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	11378394835588519530267990996949059200460406251702329283208993553778772384079	84	UVM_INFO @ 486280008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	110184027087219457855955516570665224354973585421233778639045997950746952966525	78	UVM_INFO @ 61641553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	20368627552298873928923682791747318788578179469851319981206449586562132113415	79	UVM_INFO @ 10013613128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	31127310610883262252611343918444937050562207283553820436886334936293007001135	87	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	27833957417523835456251804494821670566431076294001861737692714558455462945217	78	UVM_INFO @ 1329699468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---