Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 83.82 %
  • assert
  • 94.13 %
  • func
  • 92.83 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 79.43 %
  • toggle
  • 85.75 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.250s 55.422us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 15.898us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.940s 15.996us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.000s 83.174us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 354.246us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.810s 52.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.940s 15.996us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 354.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.020s 505.159us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.310s 1556.242us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.970s 38.465us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.930s 138.267us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.900s 440.067us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_prog_failure 1.930s 138.267us 1 1 100.00
lc_ctrl_errors 5.900s 440.067us 1 1 100.00
lc_ctrl_security_escalation 7.430s 419.858us 1 1 100.00
lc_ctrl_jtag_state_failure 25.820s 11356.935us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.050s 517.927us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 1808.257us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.320s 293.770us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.330s 899.393us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.050s 517.927us 1 1 100.00
lc_ctrl_jtag_errors 12.320s 1808.257us 1 1 100.00
lc_ctrl_jtag_access 2.570s 210.358us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.530s 1188.070us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.590s 1860.110us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.000s 153.541us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.450s 6206.053us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.720s 632.725us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.930s 26.168us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.370s 77.573us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 178.665us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.290s 213.836us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 24.280us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 106.460s 10393.640us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.930s 60.048us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 193.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 193.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 15.898us 1 1 100.00
lc_ctrl_csr_rw 0.940s 15.996us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 354.246us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 29.800us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 15.898us 1 1 100.00
lc_ctrl_csr_rw 0.940s 15.996us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 354.246us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 29.800us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
lc_ctrl_tl_intg_err 1.620s 75.675us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.620s 75.675us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.310s 1556.242us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.240s 893.024us 1 1 100.00
lc_ctrl_sec_cm 6.260s 700.848us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.430s 419.858us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.020s 505.159us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.330s 899.393us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.540s 2214.509us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.540s 2214.509us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.940s 1077.485us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.890s 280.151us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.890s 280.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 44.110s 3416.316us 1 1 100.00