Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.27 %
  • code
  • 83.58 %
  • assert
  • 94.41 %
  • func
  • 92.83 %
  • line
  • 97.13 %
  • branch
  • 93.52 %
  • cond
  • 79.41 %
  • toggle
  • 85.24 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.140s 24.169us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 59.763us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 12.520us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.370s 37.096us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 81.960us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 299.876us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 12.520us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 81.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.020s 462.511us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.460s 323.139us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.820s 14.493us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.380s 111.126us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.130s 304.354us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_prog_failure 2.380s 111.126us 1 1 100.00
lc_ctrl_errors 4.130s 304.354us 1 1 100.00
lc_ctrl_security_escalation 3.930s 405.158us 1 1 100.00
lc_ctrl_jtag_state_failure 19.220s 17799.952us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 1272.064us 1 1 100.00
lc_ctrl_jtag_errors 26.300s 3213.582us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.720s 1600.700us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.300s 291.494us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 1272.064us 1 1 100.00
lc_ctrl_jtag_errors 26.300s 3213.582us 1 1 100.00
lc_ctrl_jtag_access 3.550s 1040.302us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.540s 655.518us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.940s 88.594us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.210s 716.813us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.250s 930.747us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.280s 1262.004us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.430s 361.870us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.680s 137.062us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 66.477us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.860s 493.450us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 145.241us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 10.610s 714.797us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.970s 30.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.320s 162.151us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.320s 162.151us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 59.763us 1 1 100.00
lc_ctrl_csr_rw 0.880s 12.520us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 81.960us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 17.960us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 59.763us 1 1 100.00
lc_ctrl_csr_rw 0.880s 12.520us 1 1 100.00
lc_ctrl_csr_aliasing 1.100s 81.960us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.030s 17.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
lc_ctrl_tl_intg_err 2.120s 482.204us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.120s 482.204us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.460s 323.139us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.760s 429.461us 1 1 100.00
lc_ctrl_sec_cm 6.690s 235.519us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.930s 405.158us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.020s 462.511us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.300s 291.494us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.720s 1491.822us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.720s 1491.822us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.580s 2993.827us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.340s 1106.167us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.340s 1106.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.990s 1035.193us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 48894377360914623423669670859587556335559440840804238156445631969806690979442 2131
UVM_INFO @ 1035193327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---