Simulation Results: otbn

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.78 %
  • code
  • 81.97 %
  • assert
  • 89.90 %
  • func
  • 97.46 %
  • block
  • 97.77 %
  • line
  • 97.97 %
  • branch
  • 82.08 %
  • toggle
  • 81.62 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 139.096us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 27.000s 21.177us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 25.000s 14.309us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 30.000s 167.273us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 26.000s 72.604us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 29.000s 229.743us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 25.000s 14.309us 1 1 100.00
otbn_csr_aliasing 26.000s 72.604us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 127.000s 111324.613us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 16.000s 1097.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 32.000s 92.270us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 48.000s 738.453us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 52.000s 426.478us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 54.000s 170.305us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 19.000s 65.130us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.108us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 28.197us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 31.000s 24.858us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 6.000s 34.772us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 100.633us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 100.633us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 27.000s 21.177us 1 1 100.00
otbn_csr_rw 25.000s 14.309us 1 1 100.00
otbn_csr_aliasing 26.000s 72.604us 1 1 100.00
otbn_same_csr_outstanding 5.000s 42.635us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 27.000s 21.177us 1 1 100.00
otbn_csr_rw 25.000s 14.309us 1 1 100.00
otbn_csr_aliasing 26.000s 72.604us 1 1 100.00
otbn_same_csr_outstanding 5.000s 42.635us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 15.000s 24.413us 1 1 100.00
otbn_dmem_err 24.000s 51.780us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 30.000s 56.540us 1 1 100.00
otbn_controller_ispr_rdata_err 28.000s 17.915us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 52.737us 1 1 100.00
otbn_urnd_err 5.000s 29.424us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 13.000s 30.932us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 38.223us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 10.000s 47.934us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
otbn_tl_intg_err 12.000s 68.660us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 6.000s 32.685us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 139.096us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 24.000s 51.780us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 15.000s 24.413us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 68.660us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 19.000s 65.130us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 15.000s 24.413us 1 1 100.00
otbn_dmem_err 24.000s 51.780us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.108us 1 1 100.00
otbn_illegal_mem_acc 13.000s 30.932us 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 15.000s 24.413us 1 1 100.00
otbn_dmem_err 24.000s 51.780us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.108us 1 1 100.00
otbn_illegal_mem_acc 13.000s 30.932us 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 19.000s 65.130us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 15.000s 24.413us 1 1 100.00
otbn_dmem_err 24.000s 51.780us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 58.108us 1 1 100.00
otbn_illegal_mem_acc 13.000s 30.932us 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 23.000s 40.389us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 51.309us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 22.000s 367.761us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 22.000s 367.761us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 304.197us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 206.140us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 27.191us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 27.191us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 23.850us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 52.000s 426.478us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 23.000s 312.270us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 432.612us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 326.000s 1786.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 317.000s 1159.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 70.249us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 92349047618799261830974420469087638893980846032031512706127945209324347238148 91
UVM_INFO @ 32684958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---