Simulation Results: pwrmgr

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.45 %
  • code
  • 95.65 %
  • assert
  • 98.69 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.730s 32.417us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 65.469us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.940s 1294.778us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.930s 39.918us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.030s 57.242us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 39.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.650s 31.089us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.650s 31.089us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.770s 57.019us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 81.505us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.510s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.750s 154.277us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.510s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.870s 251.377us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.780s 181.160us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.890s 113.882us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 8.160s 10868.758us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.670s 46.945us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.940s 108.120us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.940s 108.120us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 65.469us 1 1 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 39.918us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 51.829us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 65.469us 1 1 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 39.918us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 51.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.340s 199.042us 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.340s 199.042us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 908.352us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.870s 251.377us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.670s 1252.684us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.820s 112.175us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.750s 33.688us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.110s 328.611us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.600s 33.803us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.730s 33.173us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.670s 90.971us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 149.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.750s 360.228us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.780s 2459.879us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 56529795764419231512849393132506256895827731336131783097249427771954636500172 121
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 96217959073760427710444336996440714408978239624996512290468895433457551210178 534
UVM_INFO @ 10868758173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---