| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_max_throughput_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_err_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rom_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_digest | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_local_esc | 0 | 2 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 20 test runs | |||
| rom_ctrl_smoke | 103787324358129328369704811751192125981641352406547763404186370445295731624499 | None | ||
| rom_ctrl_stress_all | 22049969201707419534619163248364835598458295721181066073782501915457761666868 | None | ||
| rom_ctrl_max_throughput_chk | 34875461573165073541235143867095664012086434388149996923138197394894875732584 | None | ||
| rom_ctrl_corrupt_sig_fatal_chk | 11693064351530082618229622771835684385518353617694380324517714273054434946105 | None | ||
| rom_ctrl_kmac_err_chk | 110129247598854306334738845812693824822930261602287158706093102347619338992389 | None | ||
| rom_ctrl_stress_all_with_rand_reset | 38166719757183917951980742589623632372241743465592956155141063566334133151318 | None | ||
| rom_ctrl_sec_cm | 4829978797500688411750609550717292516305686256805452956143652956870459765790 | None | ||
| rom_ctrl_passthru_mem_tl_intg_err | 80730199287910937583875751000737255286631718676234710852408641491225392035980 | None | ||
| rom_ctrl_tl_errors | 7844364809885509538176581199695901036363454939724325057980727770391496176099 | None | ||
| rom_ctrl_tl_intg_err | 51884504191715622632517563952323210853993935889381665199121357050759148601131 | None | ||
| rom_ctrl_alert_test | 40931451484554643075064781505235939445348550939500179821122751993394831906390 | None | ||
| rom_ctrl_mem_walk | 82047209060885787029287622042635251273895996105458219050516976559077909698097 | None | ||
| rom_ctrl_mem_partial_access | 82806361483626797938271660726470783620065132657915463222972643773002109453894 | None | ||
| rom_ctrl_csr_hw_reset | 111183984118015487636899512314577269899894676768803494348672757395368869506225 | None | ||
| rom_ctrl_csr_rw | 56150378978649805273436232084542093116694644505001774847030933028327404944870 | None | ||
| rom_ctrl_csr_bit_bash | 66534305749045449736349887051874183460902724368809011037208631456884331789076 | None | ||
| rom_ctrl_csr_aliasing | 59650857441274164039293259245731515842962881661858917626458014908756098842442 | None | ||
| rom_ctrl_same_csr_outstanding | 84443155168975831039964512774151281105746302939727245327964359169288556997331 | None | ||
| rom_ctrl_csr_mem_rw_with_rand_reset | 6973358952471320964831618464476327512028993249389733117720168694319135457035 | None | ||
| rom_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/default/fusesoc-work/184859: No such file or directory.
/tmp/vcs_20260727153209_129635/.stack_annotator_gdb_cmd_file_KqlUnY:2: Error in sourced command file:
No stack.
Process VmPeak: 437116 kb, VmSize: 421512 kb
System Free Memory: 255028744 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 11.461 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cover_reg_top/fusesoc-work/105205: No such file or directory.
/tmp/vcs_20260727153105_11238/.stack_annotator_gdb_cmd_file_nCCCCv:2: Error in sourced command file:
No stack.
Process VmPeak: 438020 kb, VmSize: 422416 kb
System Free Memory: 255135032 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 12.616 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rom_ctrl | None | None | ||