Simulation Results: rstmgr

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.25 %
  • code
  • 99.28 %
  • assert
  • 98.93 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.47 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.060s 132.446us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.850s 139.397us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.600s 2471.139us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.380s 216.194us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.030s 192.039us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00
rstmgr_csr_aliasing 1.380s 216.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.890s 172.067us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.560s 183.581us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.930s 126.365us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.420s 2186.673us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.420s 2186.673us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.420s 2186.673us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.420s 2186.673us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 14.350s 5081.566us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.840s 72.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.680s 158.690us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.680s 158.690us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 139.397us 1 1 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00
rstmgr_csr_aliasing 1.380s 216.194us 1 1 100.00
rstmgr_same_csr_outstanding 1.170s 142.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.850s 139.397us 1 1 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00
rstmgr_csr_aliasing 1.380s 216.194us 1 1 100.00
rstmgr_same_csr_outstanding 1.170s 142.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.440s 8496.140us 1 1 100.00
rstmgr_tl_intg_err 1.650s 496.792us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.440s 8496.140us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.440s 8496.140us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.650s 496.792us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.160s 188.406us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.850s 2791.043us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.140s 301.696us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.440s 8496.140us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.800s 68.273us 1 1 100.00