Simulation Results: rv_timer

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 95.29 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.940s 983.036us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.690s 18.676us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.610s 46.125us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.080s 306.301us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.920s 29.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.660s 122.345us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.610s 46.125us 1 1 100.00
rv_timer_csr_aliasing 0.920s 29.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.630s 106.124us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.250s 937.838us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 81.640s 241503.536us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 81.640s 241503.536us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.110s 1782.121us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 50.877us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 12.784us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.790s 126.204us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.790s 126.204us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.690s 18.676us 1 1 100.00
rv_timer_csr_rw 0.610s 46.125us 1 1 100.00
rv_timer_csr_aliasing 0.920s 29.085us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 127.436us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.690s 18.676us 1 1 100.00
rv_timer_csr_rw 0.610s 46.125us 1 1 100.00
rv_timer_csr_aliasing 0.920s 29.085us 1 1 100.00
rv_timer_same_csr_outstanding 0.760s 127.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.770s 244.454us 1 1 100.00
rv_timer_tl_intg_err 1.140s 265.820us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.140s 265.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.660s 103.639us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 177.540us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.690s 8957.467us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 95902994746375888206748657166476814486186417468621121850658046983183910125391 75
UVM_INFO @ 103638816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 587443145584860730010754291254959957493028692457376760125869450764465721348 75
UVM_INFO @ 106123599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 38472026799103953938942599920379998226512488553668324426786065463226487608074 75
UVM_INFO @ 177540100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---