Simulation Results: spi_device/1r1w

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.53 %
  • code
  • 93.70 %
  • assert
  • 95.40 %
  • func
  • 64.48 %
  • line
  • 98.81 %
  • branch
  • 98.06 %
  • cond
  • 95.73 %
  • toggle
  • 86.56 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 37.110s 8950.818us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.010s 74.729us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.300s 51.034us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 28.990s 67022.935us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.690s 1266.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.180s 95.463us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.300s 51.034us 1 1 100.00
spi_device_csr_aliasing 11.690s 1266.816us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.810s 20.068us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.980s 17.718us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.730s 68.591us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.840s 1.358us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.750s 3.137us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.120s 29.708us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.120s 29.708us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.590s 70067.990us 1 1 100.00
spi_device_tpm_sts_read 0.700s 53.163us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 17.560s 10714.471us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.070s 2662.204us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 432.030us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.130s 432.030us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.280s 307.781us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.280s 307.781us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.280s 307.781us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.280s 307.781us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.280s 307.781us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.630s 714.559us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.780s 6278.074us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.780s 6278.074us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.780s 6278.074us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.290s 588.046us 1 1 100.00
spi_device_read_buffer_direct 5.530s 2527.669us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.780s 6278.074us 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 148.680s 94779.621us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.680s 119.546us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.680s 119.546us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 49.410s 163119.288us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 37.110s 8950.818us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 80.240s 7781.088us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 116.650s 151034.950us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.700s 20.250us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.790s 27.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.460s 138.548us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.460s 138.548us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 74.729us 1 1 100.00
spi_device_csr_rw 1.300s 51.034us 1 1 100.00
spi_device_csr_aliasing 11.690s 1266.816us 1 1 100.00
spi_device_same_csr_outstanding 2.700s 135.839us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 74.729us 1 1 100.00
spi_device_csr_rw 1.300s 51.034us 1 1 100.00
spi_device_csr_aliasing 11.690s 1266.816us 1 1 100.00
spi_device_same_csr_outstanding 2.700s 135.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.060s 94.329us 1 1 100.00
spi_device_tl_intg_err 6.210s 326.812us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.210s 326.812us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 92115169244423963884549397167877487487335276156084729210626405678896263004128 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1038394 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1038394 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[971])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 56283712654296126479558313497311743850890692573358231537320642289277460303660 76
UVM_ERROR @ 913872 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x268 [1001101000] vs 0x0 [0])
UVM_ERROR @ 932872 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x141 [101000001] vs 0x0 [0])
UVM_ERROR @ 1014872 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x185 [110000101] vs 0x0 [0])
UVM_ERROR @ 1056872 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x296 [1010010110] vs 0x0 [0])