Simulation Results: spi_host

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.77 %
  • code
  • 91.14 %
  • assert
  • 96.79 %
  • func
  • 87.39 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
87.50%
V2
95.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
spi_host_smoke 265.000s 200000.000us 0 1 0.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 42.011us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 16.697us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 397.607us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 20.125us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 44.057us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 16.697us 1 1 100.00
spi_host_csr_aliasing 1.000s 20.125us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 17.162us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 19.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 168.785us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 63.191us 1 1 100.00
spi_host_error_cmd 2.000s 92.285us 1 1 100.00
spi_host_event 13.000s 3499.091us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 30.087us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 30.087us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 30.087us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 114.000s 3653.538us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 106.346us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 48.129us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 30.087us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 30.087us 1 1 100.00
duplex 0 1 0.00
spi_host_smoke 265.000s 200000.000us 0 1 0.00
tx_rx_only 0 1 0.00
spi_host_smoke 265.000s 200000.000us 0 1 0.00
stress_all 1 1 100.00
spi_host_stress_all 12.000s 1383.401us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 2108.599us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 19.000s 1958.359us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 105.411us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 63.191us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 48.118us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 67.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 43.512us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 43.512us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 42.011us 1 1 100.00
spi_host_csr_rw 1.000s 16.697us 1 1 100.00
spi_host_csr_aliasing 1.000s 20.125us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 25.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 42.011us 1 1 100.00
spi_host_csr_rw 1.000s 16.697us 1 1 100.00
spi_host_csr_aliasing 1.000s 20.125us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 25.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 93.014us 1 1 100.00
spi_host_sec_cm 1.000s 443.828us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 93.014us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_smoke 74195695943257221637323216323659013160588249552086878038903815768580104212568 159
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---