Simulation Results: sram_ctrl/main

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 95.70 %
  • assert
  • 97.69 %
  • func
  • 94.00 %
  • block
  • 96.09 %
  • line
  • 96.82 %
  • branch
  • 94.16 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 1398.902us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 170.710us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.909us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 113.631us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.121us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 355.667us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 13.909us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.121us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 96.000s 2994.097us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 57.000s 15022.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 31.000s 8088.967us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 8876.539us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 156.000s 18404.915us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 43.000s 11252.240us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 41.000s 31825.354us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 5882.373us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 687.267us 1 1 100.00
sram_ctrl_partial_access_b2b 211.000s 17732.317us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 660.307us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2759.950us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 677.342us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 945.467us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1305.148us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 308.000s 190212.428us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.926us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 33.185us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 33.185us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 170.710us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.909us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.121us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 170.710us 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.909us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.121us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 28240.551us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 118.693us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 118.693us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 945.467us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 945.467us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 13.909us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 5882.373us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 5882.373us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 5882.373us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 41.000s 31825.354us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 1366.557us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 28240.551us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2672.503us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1398.902us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1398.902us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 5882.373us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 41.000s 31825.354us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 1398.902us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 165.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 24458.437us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 88114414957975787368157351962458161663694621446379099616774692842018407508918 86
UVM_INFO @ 660306810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 28307416100135131985826294276912602865130475014907117520327711601246622633833 86
UVM_INFO @ 2759949826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 47565317561645834556429399592618079493032579577764276241883906464541989247779 86
UVM_INFO @ 677342113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---