Simulation Results: sysrst_ctrl

 
27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.25 %
  • code
  • 94.31 %
  • assert
  • 96.36 %
  • func
  • 56.07 %
  • line
  • 97.88 %
  • branch
  • 97.96 %
  • cond
  • 95.15 %
  • toggle
  • 99.77 %
  • FSM
  • 80.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.280s 2109.020us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.940s 2449.701us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.670s 2414.483us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.480s 2256.115us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 5.970s 6039.399us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.810s 2085.432us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 78.510s 39063.198us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.320s 2432.381us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.820s 2105.291us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.810s 2085.432us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.320s 2432.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 43.530s 23902.998us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 42.250s 24329.064us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 6.950s 3342.827us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.400s 5233.986us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.510s 2510.595us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.880s 2224.757us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.320s 3007.226us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.980s 2616.292us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 300.740s 2174095.403us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 64.150s 38617.416us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.100s 6626.314us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.590s 2038.962us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.990s 2016.203us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.490s 2135.746us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.490s 2135.746us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.970s 6039.399us 1 1 100.00
sysrst_ctrl_csr_rw 1.810s 2085.432us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.320s 2432.381us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.120s 8324.371us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 5.970s 6039.399us 1 1 100.00
sysrst_ctrl_csr_rw 1.810s 2085.432us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.320s 2432.381us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.120s 8324.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 37.940s 42039.782us 1 1 100.00
sysrst_ctrl_tl_intg_err 19.680s 22223.331us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 19.680s 22223.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.920s 12035.403us 1 1 100.00