Simulation Results

Simulation Results: uart

27/07/2026 15:30:29 DVSim: v1.50.0 sha: f1870b5 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.26 %

code
91.62 %

assert
98.56 %

func
59.59 %

line
99.17 %

branch
96.97 %

cond
95.68 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.070s	851.636us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.620s	43.234us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.820s	14.107us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.750s	171.887us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.780s	76.706us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.960s	24.629us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.820s	14.107us	1	1	100.00
	uart_csr_aliasing	0.780s	76.706us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	11.100s	13578.783us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.070s	851.636us	1	1	100.00
	uart_tx_rx	11.100s	13578.783us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	236.250s	278291.877us	1	1	100.00
	uart_rx_parity_err	19.240s	23088.473us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	11.100s	13578.783us	1	1	100.00
	uart_intr	236.250s	278291.877us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	8.170s	36312.160us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	107.720s	92104.994us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	25.000s	17530.348us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	236.250s	278291.877us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	236.250s	278291.877us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	236.250s	278291.877us	1	1	100.00
perf				1	1	100.00
	uart_perf	228.000s	7935.430us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	3.120s	6244.773us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	3.120s	6244.773us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	13.960s	44783.001us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	3.670s	42930.867us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.560s	4235.548us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	2.920s	2767.656us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	112.030s	96432.176us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	481.900s	101635.135us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.680s	51.213us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.690s	40.841us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.180s	98.317us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.180s	98.317us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.620s	43.234us	1	1	100.00
	uart_csr_rw	0.820s	14.107us	1	1	100.00
	uart_csr_aliasing	0.780s	76.706us	1	1	100.00
	uart_same_csr_outstanding	0.770s	39.082us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.620s	43.234us	1	1	100.00
	uart_csr_rw	0.820s	14.107us	1	1	100.00
	uart_csr_aliasing	0.780s	76.706us	1	1	100.00
	uart_same_csr_outstanding	0.770s	39.082us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.070s	68.992us	1	1	100.00
	uart_tl_intg_err	1.010s	55.033us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.010s	55.033us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	33.770s	7513.513us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				1 test run
	uart_noise_filter	106901719939623887930747430779337816795915922584110690670357153562908888034716	82	UVM_ERROR @ 43025360553 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 43025400553 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 43025480553 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 43025520553 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 63 [0x3f]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_stress_all_with_rand_reset	106464883602591253608578384129760432108338842080791829970354147545185044669008	174	UVM_ERROR @ 5991053007 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 6151493007 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/359 UVM_INFO @ 6258753007 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/359 UVM_INFO @ 6370188594 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]