Simulation Results: adc_ctrl

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.40 %
  • code
  • 93.84 %
  • assert
  • 92.38 %
  • func
  • 12.99 %
  • line
  • 98.74 %
  • branch
  • 97.22 %
  • cond
  • 86.97 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.220s 5868.511us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.640s 785.875us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.020s 543.888us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 51.330s 52617.527us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.390s 1159.356us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.170s 365.801us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.020s 543.888us 1 1 100.00
adc_ctrl_csr_aliasing 2.390s 1159.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.760s 277.562us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.810s 299.797us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.970s 329.410us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.120s 465.790us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.900s 505.800us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.850s 431.771us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.870s 416.804us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.940s 294.394us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.200s 3656.195us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 17.340s 23023.664us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 163.790s 108431.922us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.920s 881.706us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.690s 439.548us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.060s 362.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.980s 494.174us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.980s 494.174us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.640s 785.875us 1 1 100.00
adc_ctrl_csr_rw 1.020s 543.888us 1 1 100.00
adc_ctrl_csr_aliasing 2.390s 1159.356us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.100s 2630.155us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.640s 785.875us 1 1 100.00
adc_ctrl_csr_rw 1.020s 543.888us 1 1 100.00
adc_ctrl_csr_aliasing 2.390s 1159.356us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.100s 2630.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.430s 4897.494us 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4542.612us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.660s 4542.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 0.800s 814.983us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 100912453706114546883653964703925922721789217696781312970025212577715554754373 386
UVM_INFO @ 277562354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 35456237340135395919401456267928681405316415351315172117173903703081465853368 386
UVM_INFO @ 299797427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 79016658627697055406597176080769912547163170578523008699641914687351377787140 386
UVM_INFO @ 329410139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 26511695834109883759843858370431141008417989223919417783424515400500399950008 386
UVM_INFO @ 465789903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 11119969922228740455244068324632778166429154264288713516476805742809071740275 386
UVM_INFO @ 505800138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 88199013098327021326863989300956968625840479908763793983642363516502731371937 386
UVM_INFO @ 431771343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 114973524841156246230483232473280736441459116051289353837556141424658714187326 386
UVM_INFO @ 294394358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 17227683890270899043420722174247357242291052682757253437731933463687834031376 386
UVM_INFO @ 416804340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 43809531817216118473516920205680816989687837606299213340544940406551396557276 392
UVM_INFO @ 814983174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 56376509893596462955852543634468013219601258950860616701947303740181619902883 387
UVM_INFO @ 881705761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---