Simulation Results: aes/masked

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.30 %
  • code
  • 94.73 %
  • assert
  • 98.23 %
  • func
  • 74.95 %
  • block
  • 95.14 %
  • line
  • 96.05 %
  • branch
  • 89.33 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 63.644us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 85.140us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 56.083us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 65.534us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 912.457us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 231.670us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 66.177us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 65.534us 1 1 100.00
aes_csr_aliasing 3.000s 231.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 85.140us 1 1 100.00
aes_config_error 2.000s 77.413us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 85.140us 1 1 100.00
aes_config_error 2.000s 77.413us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_b2b 3.000s 106.576us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 85.140us 1 1 100.00
aes_config_error 2.000s 77.413us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 64.501us 1 1 100.00
aes_config_error 2.000s 77.413us 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 295.139us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 1492.430us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_sideload 2.000s 172.340us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 699.750us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 200.606us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 119.494us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 106.101us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 106.101us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 56.083us 1 1 100.00
aes_csr_rw 2.000s 65.534us 1 1 100.00
aes_csr_aliasing 3.000s 231.670us 1 1 100.00
aes_same_csr_outstanding 3.000s 388.044us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 56.083us 1 1 100.00
aes_csr_rw 2.000s 65.534us 1 1 100.00
aes_csr_aliasing 3.000s 231.670us 1 1 100.00
aes_same_csr_outstanding 3.000s 388.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 90.495us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
aes_shadow_reg_errors_with_csr_rw 2.000s 163.428us 0 1 0.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 416.453us 1 1 100.00
aes_tl_intg_err 2.000s 585.575us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 585.575us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 85.140us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
aes_core_fi 2.000s 209.242us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 77.413us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_core_fi 2.000s 209.242us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 89.310us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 88.480us 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 106.262us 1 1 100.00
aes_sideload 2.000s 172.340us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.480us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 88.480us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 88.480us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 88.480us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 88.480us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 106.262us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 433.860us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 433.860us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 433.860us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 433.860us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 7.000s 626.099us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_ctr_fi 2.000s 81.165us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 433.860us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 433.860us 0 1 0.00
aes_control_fi 1.000s 52.446us 1 1 100.00
aes_cipher_fi 2.000s 258.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 1451.965us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 89144070309494397218916929803888065518834860382725863073683052105604685002694 2354
UVM_INFO @ 90495232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 92789255894170029400065359194027948606772631368060847934176690075100918348562 15191
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 70418282066795623314053970645584528073811220640420638961538252915455756388097 205
UVM_INFO @ 1451965009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors_with_csr_rw 36724122196541934696065671862266967624827495868103780777926305830250321230420 107
UVM_INFO @ 163428340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---