Simulation Results: alert_handler

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 91.11 %
  • assert
  • 98.22 %
  • func
  • 77.53 %
  • line
  • 99.66 %
  • branch
  • 98.22 %
  • cond
  • 91.60 %
  • toggle
  • 91.88 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.740s 242.927us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.700s 426.234us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 165.070s 4545.095us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 186.880s 18939.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.450s 143.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.700s 426.234us 1 1 100.00
alert_handler_csr_aliasing 186.880s 18939.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 211.170s 25818.885us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 3.600s 72.348us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1106.100s 65479.302us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.060s 185.147us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 33.110s 4119.892us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 39.630s 2808.952us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 25.320s 3747.365us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2239.100s 334659.744us 1 1 100.00
alert_handler_lpg_stub_clk 491.000s 127702.805us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1396.410s 53213.891us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 11.210s 408.744us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.870s 63.714us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.100s 10.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.240s 85.812us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.240s 85.812us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.740s 242.927us 1 1 100.00
alert_handler_csr_rw 3.700s 426.234us 1 1 100.00
alert_handler_csr_aliasing 186.880s 18939.686us 1 1 100.00
alert_handler_same_csr_outstanding 27.450s 2609.159us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.740s 242.927us 1 1 100.00
alert_handler_csr_rw 3.700s 426.234us 1 1 100.00
alert_handler_csr_aliasing 186.880s 18939.686us 1 1 100.00
alert_handler_same_csr_outstanding 27.450s 2609.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 115.310s 5890.763us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 115.310s 5890.763us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 115.310s 5890.763us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 115.310s 5890.763us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 171.380s 8434.300us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
alert_handler_tl_intg_err 2.250s 149.197us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.250s 149.197us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 115.310s 5890.763us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 7.180s 125.569us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.060s 185.147us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2239.100s 334659.744us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.060s 185.147us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1106.100s 65479.302us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1106.100s 65479.302us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.700s 4794.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 178.340s 21457.382us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 35044104795505987110067042926883473627075858475616753667648787667057410138476 90
UVM_INFO @ 3747365485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 115117310079644048365275366871313059761002657646498096659787138085027748873394 196
UVM_INFO @ 21457382263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---