Simulation Results: chip

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.93 %
  • code
  • 81.62 %
  • assert
  • 97.37 %
  • func
  • 48.79 %
  • line
  • 94.16 %
  • branch
  • 93.64 %
  • cond
  • 89.58 %
  • toggle
  • 73.57 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.09%
V2S
50.00%
V3
57.69%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 115.840s 2843.382us 1 1 100.00
chip_sw_example_rom 99.970s 3375.990us 1 1 100.00
chip_sw_example_manufacturer 148.310s 3623.666us 1 1 100.00
chip_sw_example_concurrency 195.340s 3722.388us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 266.450s 8557.854us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 232.750s 4709.898us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 579.620s 7478.017us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3577.120s 30509.786us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 59.940s 2599.008us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3577.120s 30509.786us 1 1 100.00
chip_csr_rw 232.750s 4709.898us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 3.760s 45.373us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 288.350s 4892.435us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 288.350s 4892.435us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 288.350s 4892.435us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 274.520s 4923.765us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 274.520s 4923.765us 1 1 100.00
chip_sw_uart_tx_rx_idx1 251.150s 4533.473us 1 1 100.00
chip_sw_uart_tx_rx_idx2 274.060s 5397.287us 1 1 100.00
chip_sw_uart_tx_rx_idx3 251.990s 4309.481us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 291.880s 3916.180us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 424.460s 5027.253us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 483.490s 9046.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 225.450s 5417.667us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 225.450s 5417.667us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 148.130s 3959.735us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 133.960s 3714.299us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 180.240s 5343.649us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 1142.680s 17661.536us 1 1 100.00
chip_tap_straps_testunlock0 126.150s 3364.635us 1 1 100.00
chip_tap_straps_rma 344.970s 6179.290us 1 1 100.00
chip_tap_straps_prod 340.050s 6890.441us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 382.340s 6594.074us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 382.340s 6594.074us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 627.190s 9812.510us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 680.400s 9318.210us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.320s 4706.712us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 433.490s 5751.973us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.240s 19979.077us 1 1 100.00
chip_sw_aes_enc_jitter_en 164.710s 3988.637us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 606.640s 7873.834us 1 1 100.00
chip_sw_hmac_enc_jitter_en 145.290s 2938.572us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1520.690s 13286.280us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 164.990s 4099.480us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 268.320s 5041.144us 1 1 100.00
chip_sw_clkmgr_jitter 187.020s 3860.800us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 142.120s 3093.262us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 533.610s 12941.322us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 200.840s 5358.425us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 100.680s 3158.955us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 200.840s 5358.425us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 172.610s 3490.425us 1 1 100.00
chip_sw_aes_smoketest 181.020s 4354.736us 1 1 100.00
chip_sw_aon_timer_smoketest 211.700s 4243.094us 1 1 100.00
chip_sw_clkmgr_smoketest 185.850s 3389.527us 1 1 100.00
chip_sw_csrng_smoketest 172.190s 3385.012us 1 1 100.00
chip_sw_entropy_src_smoketest 715.020s 6497.562us 1 1 100.00
chip_sw_gpio_smoketest 177.510s 3195.278us 1 1 100.00
chip_sw_hmac_smoketest 149.970s 4124.545us 1 1 100.00
chip_sw_kmac_smoketest 131.170s 3441.939us 1 1 100.00
chip_sw_otbn_smoketest 661.340s 7162.867us 1 1 100.00
chip_sw_pwrmgr_smoketest 261.200s 8233.588us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 185.620s 7476.796us 1 1 100.00
chip_sw_rv_plic_smoketest 121.370s 3196.661us 1 1 100.00
chip_sw_rv_timer_smoketest 143.150s 3015.499us 1 1 100.00
chip_sw_rstmgr_smoketest 96.950s 3458.800us 1 1 100.00
chip_sw_sram_ctrl_smoketest 131.270s 3874.680us 1 1 100.00
chip_sw_uart_smoketest 144.110s 4163.606us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 125.630s 3746.698us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 313.000s 5732.309us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7391.860s 60540.303us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3036.680s 15590.942us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 29.454s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 759.140s 14811.447us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 714.080s 15901.602us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6281.900s 54452.920us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7203.390s 57540.998us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 63.400s 3093.365us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 63.400s 3093.365us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3577.120s 30509.786us 1 1 100.00
chip_same_csr_outstanding 2778.700s 26296.579us 1 1 100.00
chip_csr_hw_reset 266.450s 8557.854us 1 1 100.00
chip_csr_rw 232.750s 4709.898us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3577.120s 30509.786us 1 1 100.00
chip_same_csr_outstanding 2778.700s 26296.579us 1 1 100.00
chip_csr_hw_reset 266.450s 8557.854us 1 1 100.00
chip_csr_rw 232.750s 4709.898us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 7.560s 234.922us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 3.790s 55.551us 1 1 100.00
xbar_smoke_large_delays 50.740s 10193.326us 1 1 100.00
xbar_smoke_slow_rsp 31.970s 4123.287us 1 1 100.00
xbar_random_zero_delays 18.930s 291.949us 1 1 100.00
xbar_random_large_delays 61.130s 10205.815us 1 1 100.00
xbar_random_slow_rsp 207.020s 24172.468us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 9.770s 374.076us 1 1 100.00
xbar_error_and_unmapped_addr 4.540s 63.602us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 10.230s 171.187us 1 1 100.00
xbar_error_and_unmapped_addr 4.540s 63.602us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 15.140s 380.550us 1 1 100.00
xbar_access_same_device_slow_rsp 593.460s 68258.980us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 21.540s 539.589us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 139.970s 7681.031us 1 1 100.00
xbar_stress_all_with_error 139.250s 8737.283us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 320.710s 10278.037us 1 1 100.00
xbar_stress_all_with_reset_error 60.620s 294.631us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3036.680s 15590.942us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 424.770s 6703.828us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 638.420s 11692.533us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 124.539s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 12.525s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 26.302s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.192s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 7.790s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 155.832s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 17.143s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 11.710s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 10.725s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 12.754s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 58.810s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 60.917s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 66.386s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 46.760s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 47.001s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 22.060s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.270s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 21.910s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 20.030s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.900s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.350s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 24.950s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 21.210s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.890s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 19.700s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.410s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.970s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 19.350s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.640s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.000s 10.240us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 163.446s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 84.182s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 80.978s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 84.105s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 62.671s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5681.260s 32539.842us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5543.720s 30205.213us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3226.700s 17654.242us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3248.340s 16243.265us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2617.270s 35363.637us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2617.270s 35363.637us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 214.130s 4549.179us 1 1 100.00
chip_sw_aes_enc_jitter_en 164.710s 3988.637us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 166.740s 4294.141us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 161.550s 2728.280us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1047.300s 12788.500us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 203.960s 3847.143us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 442.570s 7064.649us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 508.180s 5428.890us 1 1 100.00
chip_plic_all_irqs_10 248.150s 3103.411us 1 1 100.00
chip_plic_all_irqs_20 379.420s 5424.294us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 202.680s 3493.490us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1041.010s 13539.405us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 320.970s 5429.318us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 177.980s 2942.242us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.170s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 940.070s 8176.122us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1033.690s 9139.711us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 848.760s 8468.441us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8842.230s 258176.902us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 239.660s 4426.217us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 261.200s 8233.588us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 239.660s 4426.217us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 435.030s 8816.104us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 435.030s 8816.104us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 482.530s 9486.870us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 330.350s 6412.575us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 445.860s 6395.783us 1 1 100.00
chip_sw_aes_idle 161.550s 2728.280us 1 1 100.00
chip_sw_hmac_enc_idle 120.910s 3074.392us 1 1 100.00
chip_sw_kmac_idle 102.380s 2856.224us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 359.540s 6218.967us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 381.920s 6261.892us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 275.670s 4991.459us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 324.820s 4944.040us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 982.820s 16851.209us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 404.480s 5314.314us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 396.830s 4772.290us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 424.400s 4350.723us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 387.290s 5545.093us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 482.290s 5116.483us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 414.560s 5469.104us 1 1 100.00
chip_sw_ast_clk_outputs 627.190s 9812.510us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 367.770s 7310.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 424.400s 4350.723us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 387.290s 5545.093us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.320s 4706.712us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 433.490s 5751.973us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.240s 19979.077us 1 1 100.00
chip_sw_aes_enc_jitter_en 164.710s 3988.637us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 606.640s 7873.834us 1 1 100.00
chip_sw_hmac_enc_jitter_en 145.290s 2938.572us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1520.690s 13286.280us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 164.990s 4099.480us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 268.320s 5041.144us 1 1 100.00
chip_sw_clkmgr_jitter 187.020s 3860.800us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 162.950s 3727.565us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 329.900s 5055.760us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 494.050s 7379.605us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3931.850s 25418.456us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 175.530s 3500.458us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 126.220s 3830.986us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 770.130s 11641.628us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 149.320s 3982.252us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 262.230s 6244.757us 1 1 100.00
chip_sw_flash_init_reduced_freq 997.800s 22037.562us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3975.270s 30898.448us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 627.190s 9812.510us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 362.700s 4904.671us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 255.750s 3220.023us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 940.070s 8176.122us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2291.820s 24052.349us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 273.150s 5087.253us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 514.040s 9705.208us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 179.470s 2974.063us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3061.630s 18445.573us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 131.840s 3199.659us 1 1 100.00
chip_sw_edn_entropy_reqs 534.740s 6310.291us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 131.840s 3199.659us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2291.820s 24052.349us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 178.670s 4058.881us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1120.940s 28257.778us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 460.680s 6036.051us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 433.490s 5751.973us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 288.730s 4898.526us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 335.320s 4706.712us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3293.380s 43935.594us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1120.940s 28257.778us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 201.970s 4372.697us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3293.380s 43935.594us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 226.630s 6286.971us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 468.120s 6094.177us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 371.150s 6042.903us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 371.150s 6042.903us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 115.590s 2990.717us 1 1 100.00
chip_sw_hmac_enc_jitter_en 145.290s 2938.572us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 120.910s 3074.392us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1053.440s 10611.972us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1422.340s 12018.676us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 338.090s 6258.456us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 298.320s 5098.923us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 359.850s 6282.477us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 185.350s 4053.201us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1520.690s 13286.280us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1094.640s 12277.215us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1047.300s 12788.500us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4199.580s 20026.896us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 110.310s 2875.626us 1 1 100.00
chip_sw_kmac_mode_kmac 141.910s 3787.942us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 164.990s 4099.480us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 119.060s 3524.328us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 923.150s 9232.256us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 102.380s 2856.224us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 442.570s 7064.649us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 1142.680s 17661.536us 1 1 100.00
chip_tap_straps_rma 344.970s 6179.290us 1 1 100.00
chip_tap_straps_prod 340.050s 6890.441us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 131.960s 3457.501us 1 1 100.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 721.110s 8500.922us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 22 81.82
chip_sw_flash_ctrl_lc_rw_en 184.680s 4050.638us 0 1 0.00
chip_sw_flash_rma_unlocked 3293.380s 43935.594us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 171.430s 4113.432us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 481.680s 8300.037us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 375.210s 7426.756us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 403.220s 7070.024us 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 275.320s 9705.429us 1 1 100.00
chip_sw_sram_ctrl_execution_main 446.770s 11310.732us 1 1 100.00
chip_prim_tl_access 226.630s 6286.971us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 367.770s 7310.727us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 404.480s 5314.314us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 396.830s 4772.290us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 424.400s 4350.723us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 387.290s 5545.093us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 482.290s 5116.483us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 414.560s 5469.104us 1 1 100.00
chip_tap_straps_dev 1142.680s 17661.536us 1 1 100.00
chip_tap_straps_rma 344.970s 6179.290us 1 1 100.00
chip_tap_straps_prod 340.050s 6890.441us 1 1 100.00
chip_rv_dm_lc_disabled 55.030s 2386.903us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 156.000s 4995.960us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 80.860s 4026.912us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 79.480s 3650.088us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 145.860s 4412.099us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1652.400s 38982.828us 1 1 100.00
chip_rv_dm_lc_disabled 55.030s 2386.903us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 823.320s 15019.791us 0 1 0.00
chip_sw_lc_walkthrough_prod 757.680s 13306.184us 0 1 0.00
chip_sw_lc_walkthrough_prodend 590.690s 15877.858us 1 1 100.00
chip_sw_lc_walkthrough_rma 433.120s 8981.319us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1652.400s 38982.828us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 90.830s 2998.877us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 86.570s 2888.030us 1 1 100.00
rom_volatile_raw_unlock 24.746s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3800.550s 18122.099us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3921.240s 19979.077us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 445.860s 6395.783us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 445.860s 6395.783us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 445.860s 6395.783us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 244.060s 4581.187us 1 1 100.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1120.940s 28257.778us 1 1 100.00
chip_sw_otbn_mem_scramble 244.060s 4581.187us 1 1 100.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 348.190s 7765.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 108.550s 3207.546us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1120.940s 28257.778us 1 1 100.00
chip_sw_otbn_mem_scramble 244.060s 4581.187us 1 1 100.00
chip_sw_keymgr_key_derivation 979.050s 10583.938us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 348.190s 7765.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 108.550s 3207.546us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 349.600s 7386.512us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 131.960s 3457.501us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 4 6 66.67
chip_sw_otp_ctrl_lc_signals_test_unlocked0 171.430s 4113.432us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 481.680s 8300.037us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 375.210s 7426.756us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 403.220s 7070.024us 0 1 0.00
chip_sw_lc_ctrl_transition 733.480s 26681.218us 0 1 0.00
chip_prim_tl_access 226.630s 6286.971us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 226.630s 6286.971us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 852.610s 9084.366us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 166.290s 6474.400us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 914.790s 30677.356us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 220.110s 7862.525us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 246.630s 7868.470us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 307.720s 6972.569us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 819.090s 29828.766us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 205.000s 5554.886us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 435.030s 8816.104us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1109.460s 17526.818us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 260.340s 6136.362us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 166.290s 6474.400us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 281.720s 6595.950us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 848.800s 15256.318us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 239.990s 8402.995us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 131.570s 3482.177us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 196.800s 5737.970us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 584.180s 10018.321us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1159.730s 13966.273us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1893.170s 32205.784us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 147.050s 3872.674us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 275.320s 9705.429us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 275.320s 9705.429us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1159.730s 13966.273us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 196.800s 5737.970us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 260.340s 6136.362us 1 1 100.00
chip_sw_pwrmgr_smoketest 261.200s 8233.588us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 365.730s 5349.691us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 401.170s 9474.207us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 195.240s 3962.690us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1041.010s 13539.405us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 139.960s 3855.885us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1033.690s 9139.711us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 326.260s 5058.998us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 334.360s 5025.309us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 144.880s 3804.323us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 108.550s 3207.546us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 401.170s 9474.207us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 401.170s 9474.207us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 103.930s 2710.674us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 595.670s 11311.744us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1019.260s 17164.481us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 365.730s 5349.691us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 142.010s 3512.420us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 939.770s 13901.382us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 344.970s 6179.290us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 55.030s 2386.903us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 508.180s 5428.890us 1 1 100.00
chip_plic_all_irqs_10 248.150s 3103.411us 1 1 100.00
chip_plic_all_irqs_20 379.420s 5424.294us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 152.710s 4485.361us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 166.600s 4333.195us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3036.680s 15590.942us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 255.900s 6004.060us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 150.780s 3182.953us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 155.700s 3946.618us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 119.230s 3757.089us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 348.190s 7765.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 268.320s 5041.144us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 373.970s 10766.801us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 414.360s 10846.706us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 446.770s 11310.732us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
chip_sw_data_integrity_escalation 382.340s 6594.074us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 584.180s 10018.321us 1 1 100.00
chip_sw_sysrst_ctrl_reset 794.710s 24480.482us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 123.560s 3003.120us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 189.760s 3842.434us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 265.680s 4864.902us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 794.710s 24480.482us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 794.710s 24480.482us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2379.430s 20186.414us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2379.430s 20186.414us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 261.570s 7844.300us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2617.270s 35363.637us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 140.060s 4259.619us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 115.510s 3299.675us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 215.570s 3978.324us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 247.070s 4861.461us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 712.210s 9420.906us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4881.660s 32071.697us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1861.340s 12708.452us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 129.990s 3199.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 262.720s 4372.006us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 145.150s 3875.776us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9387.280s 68571.353us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1157.710s 7003.010us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 258.920s 5006.724us 0 1 0.00
rom_e2e_jtag_debug_dev 223.730s 5588.674us 0 1 0.00
rom_e2e_jtag_debug_rma 219.930s 5163.313us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 127.830s 4401.832us 0 1 0.00
rom_e2e_jtag_inject_dev 80.410s 2665.811us 0 1 0.00
rom_e2e_jtag_inject_rma 77.500s 2523.304us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 40.221s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 307.920s 3457.831us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 312.750s 3195.595us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1119.640s 8415.990us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1083.240s 10580.134us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 207.140s 2610.712us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 487.060s 6076.786us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 130.970s 2977.228us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 144.540s 2894.838us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 245.700s 8164.660us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 219.020s 6072.906us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1159.730s 13966.273us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 258.920s 5006.724us 0 1 0.00
rom_e2e_jtag_debug_dev 223.730s 5588.674us 0 1 0.00
rom_e2e_jtag_debug_rma 219.930s 5163.313us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 171.630s 4489.083us 0 1 0.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 425.140s 5622.615us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 4767.360s 38647.304us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 4767.360s 38647.304us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 146.640s 4320.275us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 274.520s 4923.765us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2835.270s 19622.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 196.020s 3700.391us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 17.460s 10.160us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.980s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 125.490s 2897.033us 1 1 100.00
chip_sw_otp_ctrl_descrambling 159.520s 3241.608us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 184.770s 3671.582us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 6.811s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 179.790s 3860.631us 1 1 100.00
ate_bootstrap_flash_erase 616.960s 10010.120us 0 1 0.00
ate_bootstrap_one_frame 5920.840s 44074.837us 1 1 100.00
ate_bootstrap_disjoint 8933.470s 79607.364us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 111939452807497669587480978318851074899436872945293066724641375315975884530618 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 57300158091219886870524064392576545855910892692573492403269018736554467642590 None
Another command (pid=452598) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=520622) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=459954) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 22918954414749544748825417324948210865211195337346351009083543266591494933773 None
Another command (pid=592829) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=600434) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=464915) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 6700443149889412970106702440491724882129548382953920304728498529948617710836 None
Another command (pid=612429) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=642240) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=627563) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 108298381836014183397371649028017439812960240799764331252377164880282990686326 None
Another command (pid=584760) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=583870) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=592151) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 13119339291080593361818059392687045198328281243461103862371266660553307869586 None
---- STDERR ----
Another command (pid=592151) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 54678967186764752018034823956244798215412729162665526226177875134361841290520 None
Another command (pid=622148) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=626657) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=616240) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 49747288034756645159125608578240140101644198985073520493065452020139913190407 None
Another command (pid=497278) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=552004) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=560390) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 17711698712786267667300244971174599782217870402201408366774518051272636071700 None
Another command (pid=584760) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=592151) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=601631) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 36585574474242964223689818247045824548814755665418247310781189920358890985456 None
Another command (pid=584760) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=583870) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=592151) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 30666639992911329654473602689757573887781461488900224807524314672021131905640 None
Another command (pid=594259) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=600434) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=464915) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 114296378802871548256440625321378911890417595491632234964055624527468401210227 None
---- STDERR ----
Another command (pid=454773) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6241936469530845832903105221115211859867555831635090766954077952879156674117 None
---- STDERR ----
Another command (pid=552004) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=560390) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 109763381039670164642215799404605830819992685889456886768170306467859276001446 None
Another command (pid=584760) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=583870) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=592151) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 46651226710597018402886792000318332081247938552771149401677994920247694146256 None
Another command (pid=459954) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=403943) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=497278) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 76900764434896501278784278498004127706621377777711041474025580079997762772918 None
Another command (pid=506112) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=429673) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=576653) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 7166575715438037352664028601726768196218484029339835035310816164157171703401 None
Another command (pid=614290) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=632593) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=638581) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 60468872283843603857460879957652510375150993695514860913070960828364027789665 None
Another command (pid=497278) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=552004) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=560390) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 38504512643209010778965220475911998686475929031350033068372992182684553630112 None
Another command (pid=452598) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=520622) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=459954) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 79821227926306850377729351924113618070551279419454330407922237455485634199598 None
Another command (pid=560390) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=379539) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=579524) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 58212446693963749327276645958578687164698755084557674500189620964894315347773 None
---- STDERR ----
Another command (pid=459011) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 103614605018262879422578314911764332451019433443633616116554167038975195934414 None
---- STDERR ----
Another command (pid=378124) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 77665896656403987623887977302386200555490285124017820820339588352800349701193 None
Another command (pid=378124) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=426120) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=415465) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 31888893765371339675577022854082477260144150105409065886265385887745636715819 None
Another command (pid=378124) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=426120) is running. Waiting for it to complete on the server (server_pid=268281)...
Another command (pid=415465) is running. Waiting for it to complete on the server (server_pid=268281)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Offending '(rstreqs[*] && (reset_cause == HwReq))' 6 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 66809016575288682354665878451627853902475022058818513163789628921485073739354 321
UVM_ERROR @ 5737.970000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5737.970000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 8015839265317165174216992278532044771476882106165902068359335899803069894149 320
UVM_ERROR @ 5554.886000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5554.886000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 76271390012659196466510968554047664699511696833918364077778275057924111764318 331
UVM_ERROR @ 7868.470000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7868.470000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 89600519811145875482093707789146005486341470006790440615907220381442068593443 359
UVM_ERROR @ 15256.318000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 15256.318000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 17222953690419455733788061189954222569638338693095907911327584929523548918531 340
UVM_ERROR @ 24480.482000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24480.482000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 22665699767500194752353885502592003162302130832273442535932232107176894614949 325
UVM_ERROR @ 8816.104000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8816.104000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 88294306219458267157994697349415350800390399899040327589833268846495865758339 333
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 104416995468516617316774794265467682425960619228004968895972907779029735017918 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 5950963057780053243702517072798905230826843608261481630279920748356366556986 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 87906368410410928919270468745741581667271538590317748044497390105668794691408 311
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 43258151851667227211627460971885291188386314589941451356049404494449141718787 309
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 10876444185287862124706249881637939743615207339107171690200902658712419156281 309
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 1159628958904978980840369177107188250099602129337806201930727936669285956418 374
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 16226689197737842878525664256285033871188981348356655576939263677600688284360 374
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 82108618100832226789742527111080487507389314197079344906177879921089642705037 371
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 81143593109775709415611019190056700906725267131740132215654366268254875968906 334
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 22031987418267422963431993407682952993578711375918095707224521311262420100137 334
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 56561639501574879699977443957842172312495024789589134191787710692961749345832 334
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 61195020771204640938609803092968201965493069055906300199936787422232227844823 370
UVM_INFO @ 15019.791278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 86671972200581264408704494129210381395300147056989153684524517476325428108847 370
UVM_INFO @ 13306.184430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 4739961342966913484473405796132785300396031184625699142552058754232488439722 342
UVM_INFO @ 8981.318508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 63097608628681496646222592252497549739478082137545761896906892498977578031317 326
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 10385938395891043037950157165802297652634433091627156544345311386602841995042 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 88471287133173107819851507560651555673066728661524799802029090170503569531289 329
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 101909250529214021287841816395720380770033584332157164423442620863614740073046 390
UVM_INFO @ 12018.676308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 60555135587215935917087447067532717422271365757579853384309358861249280289998 342
UVM_INFO @ 20026.895957 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 26836432499462781140267189374190256734079101949350245591996118243820383005462 223
TL item was: req: (cip_tl_seq_item@32322) { a_addr: 'h10548 a_data: 'h66744bb4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1ae82 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3093.365028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 92141502483786512428619924904982875412615985941885314691743396320068656051086 230
TL item was: req: (cip_tl_seq_item@30808) { a_addr: 'h1063c a_data: 'h30f1f7ec a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1bac2 d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2599.007980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20311944145886545584982714483760748657049483668509998704407999575807817984694 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 94816817644140081693645919705780197667362593717874446757443773081168337741754 331
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 26090618792907982052775578693563298051705521629451936076689951303537400628405 374
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 49864141325949881439163798136046841685643649994515974710205245764304323340542 334
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 53548542859222999187910733280497167750447291054994965111302524385514173257301 307
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 33817097730516248068214332734445552358390523549819105913983272064874670505876 333
UVM_INFO @ 3182.953405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 79720516097032813815409655745585185660828432926569933851002360179834573269571 315
UVM_INFO @ 4050.638386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 86980329670615501288764760361508859155299159952531602152857968738139211763553 348
UVM_INFO @ 7070.023776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 77653804673730484600068268348467300633315877329021448070125736265466336517336 322
UVM_ERROR @ 2894.837970 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2894.837970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 5301222193625339912091222952608482869147523850099168794963241622166551027003 283
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 23973701867612833374257769054961772788154117719155807211680666560387539096547 311
UVM_INFO @ 26681.217519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 26719185444931343088393363046014244746813158852874908965968863658386032532303 326
UVM_ERROR @ 6474.399554 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6474.399554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 113754886592828299169771354785011627760576732831618140576893105491711786782024 319
UVM_ERROR @ 3482.177072 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3482.177072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 38633125081290052475209147655343985869231837961429455664834736309983952836594 338
UVM_INFO @ 35363.636835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:346)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 9707666491271133867254519327850844228034465845975812132129932415239276898465 313
UVM_INFO @ 3847.143024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 23286878830840175208832275281362406487490462888833512185629078870710003315259 309
UVM_INFO @ 2942.241586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 81782951508590792603278615802928621788823669614783031526650585197104622677454 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 78546214297496070491135256810116034472234104584898409159218989971562747517651 344
UVM_INFO @ 3457.830947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 57206507541683963501718847877799957178705670861213002102890852069792493303025 322
UVM_INFO @ 8164.659891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 70902754403022630676194951159337785492953521001882438926948450175951791105643 335
UVM_INFO @ 13901.381778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 57842520431314242122339807431383058440852952375777363918778250085629874096455 317
UVM_ERROR @ 4489.082976 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 4489.082976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 81313244602378396764987983752791159260817617501805282944375236749607964867307 221
UVM_INFO @ 2386.902945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 93511529316801897260508463763404138735985700383255744639382972521550480625930 335
UVM_INFO @ 3875.776137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 7094396935749507644565356409141269226446208930987744037266519971851345729426 324
UVM_INFO @ 14811.447121 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 64840039419895564388894474587089905262784912846562127434367040542877617231127 335
UVM_INFO @ 15901.601917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 55231360834134734945994510653480680936681465925736933442005395034019107020128 333
UVM_INFO @ 9318.209549 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 26467289463220869465806284659676855353870354460439543974629846069013400859621 273
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 28537112113673424644321792403869355193225514879874708301741204805846333311228 325
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 11692.533451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 110303842873987769164636424367486675721383729890980067429977631687893670669248 318
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6703.828085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 5962946421589709353564708909337926080774796308511024991649028277993728508092 331
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 49098457067758780613980939579294142587529515133186078271559206474132121796784 334
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_dev 26711546228464798665066421732036329926895838123689839443178662920353743278230 319
UVM_INFO @ 5588.674304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 25458698794273916258033542255650255607205956863073531892246184102608932294198 320
UVM_INFO @ 17654.241832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 39034397308187232346373226769843529727498274933748018765160235333748121911316 333
UVM_ERROR @ 5732.308636 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5732.308636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---