Simulation Results: clkmgr

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.71 %
  • code
  • 97.99 %
  • assert
  • 94.21 %
  • func
  • 85.93 %
  • line
  • 99.09 %
  • branch
  • 98.85 %
  • cond
  • 92.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.950s 30.507us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 16.111us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.660s 2948.803us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.110s 80.980us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.010s 94.149us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
clkmgr_csr_aliasing 1.110s 80.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.800s 59.022us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.890s 60.244us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.740s 28.381us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.640s 16.810us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.950s 30.507us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.590s 2775.987us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.300s 136.816us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.590s 2775.987us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.200s 509.060us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.710s 31.211us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.460s 65.157us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.460s 65.157us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 16.111us 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
clkmgr_csr_aliasing 1.110s 80.980us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 185.861us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 16.111us 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
clkmgr_csr_aliasing 1.110s 80.980us 1 1 100.00
clkmgr_same_csr_outstanding 1.350s 185.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 4.120s 1247.075us 1 1 100.00
clkmgr_tl_intg_err 1.710s 227.306us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 137.501us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 137.501us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 137.501us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 137.501us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 832.980s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.710s 227.306us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.590s 2775.987us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.300s 136.816us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.370s 137.501us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.090s 31.552us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.180s 65.136us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.890s 67.887us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.840s 21.866us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.850s 97.686us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.120s 1247.075us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.730s 30.244us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.120s 1247.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.180s 627.437us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 29.600s 7496.589us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 11926530568376074531300652229836655923065259042160772628077855421497840255018 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---