Simulation Results: csrng

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.90 %
  • code
  • 92.23 %
  • assert
  • 94.10 %
  • func
  • 77.37 %
  • block
  • 96.99 %
  • line
  • 97.62 %
  • branch
  • 92.51 %
  • toggle
  • 93.10 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 41.326us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 57.406us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 137.644us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 342.683us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 93.419us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 24.753us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 137.644us 1 1 100.00
csrng_csr_aliasing 3.000s 93.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 335.637us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 6.000s 97.731us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 6.000s 97.731us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 459.000s 12800.338us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 102.245us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 22.111us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 66.224us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 66.224us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 57.406us 1 1 100.00
csrng_csr_rw 3.000s 137.644us 1 1 100.00
csrng_csr_aliasing 3.000s 93.419us 1 1 100.00
csrng_same_csr_outstanding 1.000s 36.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 57.406us 1 1 100.00
csrng_csr_rw 3.000s 137.644us 1 1 100.00
csrng_csr_aliasing 3.000s 93.419us 1 1 100.00
csrng_same_csr_outstanding 1.000s 36.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
csrng_tl_intg_err 5.000s 155.421us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 28.726us 0 1 0.00
csrng_csr_rw 3.000s 137.644us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 335.637us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 459.000s 12800.338us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 335.637us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 459.000s 12800.338us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 335.637us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 155.421us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
csrng_sec_cm 3.000s 260.799us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 145.791us 1 1 100.00
csrng_err 3.000s 68.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 69110031914176903836167823103531888277733566555408116579167331641151894408005 100
UVM_INFO @ 97730515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 529109483872157032286560958980654556597835530035175605565393760412167474475 99
UVM_INFO @ 28725682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 108516391507523632003820491496285519025944655299995494300240601561498152413161 None