Simulation Results: edn/edn0

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 84.30 %
  • assert
  • 96.31 %
  • func
  • 82.74 %
  • line
  • 97.99 %
  • branch
  • 93.17 %
  • cond
  • 86.54 %
  • toggle
  • 86.82 %
  • FSM
  • 56.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 26.513us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.030s 30.829us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 44.247us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.880s 48.623us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 36.332us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 25.860us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 44.247us 1 1 100.00
edn_csr_aliasing 1.320s 36.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.110s 54.128us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.110s 54.128us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.110s 54.128us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 54.897us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 32.285us 1 1 100.00
errs 1 1 100.00
edn_err 1.010s 39.827us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 11.003us 1 1 100.00
edn_disable_auto_req_mode 1.290s 64.453us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.400s 920.470us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 14.620us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.210s 21.681us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.680s 430.577us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.680s 430.577us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.030s 30.829us 1 1 100.00
edn_csr_rw 0.830s 44.247us 1 1 100.00
edn_csr_aliasing 1.320s 36.332us 1 1 100.00
edn_same_csr_outstanding 1.000s 16.647us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.030s 30.829us 1 1 100.00
edn_csr_rw 0.830s 44.247us 1 1 100.00
edn_csr_aliasing 1.320s 36.332us 1 1 100.00
edn_same_csr_outstanding 1.000s 16.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
edn_tl_intg_err 1.260s 559.343us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 51.982us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 32.285us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.280s 32.285us 1 1 100.00
edn_sec_cm 3.920s 318.850us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 32.285us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.260s 559.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.230s 7386.472us 1 1 100.00