Simulation Results: edn/edn1

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.20 %
  • code
  • 83.71 %
  • assert
  • 98.70 %
  • func
  • 79.20 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 88.62 %
  • toggle
  • 95.06 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 52.759us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 21.405us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 23.186us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.290s 551.472us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.920s 15.245us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 339.137us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 23.186us 1 1 100.00
edn_csr_aliasing 0.920s 15.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 225.021us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 225.021us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 225.021us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 20.329us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 104.283us 1 1 100.00
errs 1 1 100.00
edn_err 0.770s 25.717us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 37.366us 1 1 100.00
edn_disable_auto_req_mode 0.900s 107.170us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.870s 1248.050us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 25.230us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 20.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.480s 273.751us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.480s 273.751us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 21.405us 1 1 100.00
edn_csr_rw 0.830s 23.186us 1 1 100.00
edn_csr_aliasing 0.920s 15.245us 1 1 100.00
edn_same_csr_outstanding 1.140s 43.530us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 21.405us 1 1 100.00
edn_csr_rw 0.830s 23.186us 1 1 100.00
edn_csr_aliasing 0.920s 15.245us 1 1 100.00
edn_same_csr_outstanding 1.140s 43.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
edn_tl_intg_err 1.640s 275.452us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 57.094us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 104.283us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 104.283us 1 1 100.00
edn_sec_cm 3.770s 342.793us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 104.283us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.640s 275.452us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 14.780s 9376.311us 1 1 100.00