Simulation Results: entropy_src/rng_4bits

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.65 %
  • code
  • 88.45 %
  • assert
  • 84.73 %
  • func
  • 53.77 %
  • block
  • 94.43 %
  • line
  • 97.11 %
  • branch
  • 86.58 %
  • toggle
  • 76.38 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 32.933us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 32.059us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 107.056us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 236.508us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 64.597us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 40.100us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 107.056us 1 1 100.00
entropy_src_csr_aliasing 4.000s 64.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 32.933us 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
entropy_src_fw_ov 39.000s 14075.693us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 39.000s 14075.693us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 170.000s 13119.399us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
entropy_src_intr 3.000s 176.372us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
entropy_src_functional_alerts 5.000s 356.797us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 192.000s 13213.541us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 86.630us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 26.063us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 114.228us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 128.558us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 128.558us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 32.059us 1 1 100.00
entropy_src_csr_rw 2.000s 107.056us 1 1 100.00
entropy_src_csr_aliasing 4.000s 64.597us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 1359.026us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 32.059us 1 1 100.00
entropy_src_csr_rw 2.000s 107.056us 1 1 100.00
entropy_src_csr_aliasing 4.000s 64.597us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 1359.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 280.543us 1 1 100.00
entropy_src_tl_intg_err 3.000s 117.553us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
entropy_src_cfg_regwen 2.000s 22.534us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
entropy_src_fw_ov 39.000s 14075.693us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
entropy_src_sec_cm 2.000s 280.543us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
entropy_src_sec_cm 2.000s 280.543us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 227.000s 14051.305us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
entropy_src_sec_cm 2.000s 280.543us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
entropy_src_sec_cm 2.000s 280.543us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 41.291us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 356.797us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 117.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 186.000s 13045.297us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 13.000s 827.934us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 112096419372421993824538843397366780369347016290849262165697521927320388022146 217
UVM_INFO @ 827933650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 57638358088589256287428219057698693081838335889927429510051940692154964445963 113
UVM_INFO @ 40099716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---