| V1 |
|
100.00% |
| V2 |
|
98.28% |
| V2S |
|
95.83% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 29.610s | 31.880us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 10.460s | 30.034us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 15.180s | 68.365us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 27.350s | 1911.717us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 23.220s | 780.875us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 9.580s | 39.267us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 23.220s | 780.875us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 5.280s | 56.497us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 5.380s | 64.330us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 10.620s | 30.156us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 42.000s | 251.003us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1160.490s | 167599.370us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 555.740s | 80135.055us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 5.410s | 74.002us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1158.190s | 702483.330us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 162.950s | 5845.726us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 5.520s | 22.363us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1635.360s | 109073.710us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 44.150s | 763.644us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 13.780s | 51.431us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 13.720s | 33.688us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 15.110s | 69.686us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 71.880s | 64.403us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 71.880s | 64.403us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 119.000s | 19746.735us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.040s | 143.285us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 567.610s | 6266.281us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 359.100s | 5420.596us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 353.770s | 8015.192us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 939.580s | 4152.261us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 5.880s | 194.988us | 1 | 1 | 100.00 | |
| read_write_overflow | 0 | 1 | 0.00 | |||
| flash_ctrl_oversize_error | 3603.684s | 0.000us | 0 | 1 | 0.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 10.420s | 65.559us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 7.910s | 79.344us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 450.480s | 4322.628us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 46.830s | 1773.271us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 53.870s | 39.813us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1160.490s | 167599.370us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 52.170s | 432.759us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 34.640s | 2831.535us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 133.630s | 49277.104us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 117.020s | 28865.650us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 31.950s | 9357.116us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 32.570s | 1605.465us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 8.940s | 105.951us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 62.170s | 907.449us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 119.710s | 2862.476us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 100.160s | 1509.027us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 377.910s | 28574.633us | 1 | 1 | 100.00 | |
| single_bit_err | 3 | 3 | 100.00 | |||
| flash_ctrl_read_word_sweep_serr | 9.800s | 30.825us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 55.180s | 2226.282us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 113.440s | 15607.847us | 1 | 1 | 100.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 51.060s | 4920.756us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 48.310s | 4280.700us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 115.730s | 31446.905us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 6.130s | 83.055us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 5.850s | 52.761us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 52.560s | 1328.822us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 259.780s | 4671.595us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 23.370s | 6205.996us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 500.940s | 168290.763us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 23.620s | 10085.617us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 6.350s | 54.092us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 5.340s | 61.605us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.680s | 67.674us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.680s | 67.674us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 15.180s | 68.365us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 23.220s | 780.875us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 6.170s | 69.600us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 15.180s | 68.365us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 23.220s | 780.875us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 6.170s | 69.600us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 27.320s | 206.039us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| flash_ctrl_tl_intg_err | 360.660s | 3981.262us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 360.660s | 3981.262us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 360.660s | 3981.262us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 14.280s | 142.974us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 6.020s | 92.993us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 29.610s | 31.880us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 53.870s | 39.813us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 10.420s | 65.559us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 34.470s | 2286.397us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 7.910s | 79.344us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 8.170s | 76.252us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 10.020s | 206.868us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 18.760s | 99.702us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 10.420s | 65.559us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 14.280s | 142.974us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 6.240s | 39.684us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 15.670s | 29.310us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 10.420s | 65.559us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 12.040s | 143.285us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 259.780s | 4671.595us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_serr | 113.440s | 15607.847us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 119.710s | 2862.476us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 377.910s | 28574.633us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1160.490s | 167599.370us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 8.920s | 653.761us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 0 | 1 | 0.00 | |||
| flash_ctrl_phy_host_grant_err | 5.430s | 6.215us | 0 | 1 | 0.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 5.720s | 74.456us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1696.460s | 7718.203us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 19.310s | 332.008us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 75.390s | 177.795us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 1 test run | |||
| flash_ctrl_oversize_error | 107610904647281100377372407630798792469116779375564004164401352024701264964727 | None | ||
| Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' | 1 test run | |||
| flash_ctrl_phy_host_grant_err | 48872031523728395297370715996675932217102501678774253117933875009903078751571 | 130 |
UVM_ERROR @ 6215.4 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 6215.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|