Simulation Results: hmac

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.90 %
  • code
  • 97.07 %
  • assert
  • 97.60 %
  • func
  • 42.03 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.67 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.330s 42.911us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 33.284us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.760s 41.302us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.670s 1688.289us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.720s 10265.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.010s 68.364us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.760s 41.302us 1 1 100.00
hmac_csr_aliasing 5.720s 10265.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 62.090s 9265.866us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 72.870s 2489.243us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.400s 472.645us 1 1 100.00
hmac_test_sha384_vectors 424.340s 22534.882us 1 1 100.00
hmac_test_sha512_vectors 339.930s 34623.608us 1 1 100.00
hmac_test_hmac256_vectors 8.180s 803.181us 1 1 100.00
hmac_test_hmac384_vectors 6.120s 1053.445us 1 1 100.00
hmac_test_hmac512_vectors 7.770s 1306.188us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.270s 10413.292us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 191.340s 3292.818us 1 1 100.00
error 1 1 100.00
hmac_error 25.700s 3862.164us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 81.190s 55092.515us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.330s 42.911us 1 1 100.00
hmac_long_msg 62.090s 9265.866us 1 1 100.00
hmac_back_pressure 72.870s 2489.243us 1 1 100.00
hmac_datapath_stress 191.340s 3292.818us 1 1 100.00
hmac_burst_wr 15.270s 10413.292us 1 1 100.00
hmac_stress_all 10.860s 1469.242us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.330s 42.911us 1 1 100.00
hmac_long_msg 62.090s 9265.866us 1 1 100.00
hmac_back_pressure 72.870s 2489.243us 1 1 100.00
hmac_datapath_stress 191.340s 3292.818us 1 1 100.00
hmac_wipe_secret 81.190s 55092.515us 1 1 100.00
hmac_test_sha256_vectors 7.400s 472.645us 1 1 100.00
hmac_test_sha384_vectors 424.340s 22534.882us 1 1 100.00
hmac_test_sha512_vectors 339.930s 34623.608us 1 1 100.00
hmac_test_hmac256_vectors 8.180s 803.181us 1 1 100.00
hmac_test_hmac384_vectors 6.120s 1053.445us 1 1 100.00
hmac_test_hmac512_vectors 7.770s 1306.188us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.330s 42.911us 1 1 100.00
hmac_long_msg 62.090s 9265.866us 1 1 100.00
hmac_back_pressure 72.870s 2489.243us 1 1 100.00
hmac_datapath_stress 191.340s 3292.818us 1 1 100.00
hmac_burst_wr 15.270s 10413.292us 1 1 100.00
hmac_error 25.700s 3862.164us 1 1 100.00
hmac_wipe_secret 81.190s 55092.515us 1 1 100.00
hmac_test_sha256_vectors 7.400s 472.645us 1 1 100.00
hmac_test_sha384_vectors 424.340s 22534.882us 1 1 100.00
hmac_test_sha512_vectors 339.930s 34623.608us 1 1 100.00
hmac_test_hmac256_vectors 8.180s 803.181us 1 1 100.00
hmac_test_hmac384_vectors 6.120s 1053.445us 1 1 100.00
hmac_test_hmac512_vectors 7.770s 1306.188us 1 1 100.00
hmac_stress_all 10.860s 1469.242us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 10.860s 1469.242us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.570s 11.987us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.580s 21.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.190s 455.390us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.190s 455.390us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 33.284us 1 1 100.00
hmac_csr_rw 0.760s 41.302us 1 1 100.00
hmac_csr_aliasing 5.720s 10265.612us 1 1 100.00
hmac_same_csr_outstanding 1.830s 140.936us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 33.284us 1 1 100.00
hmac_csr_rw 0.760s 41.302us 1 1 100.00
hmac_csr_aliasing 5.720s 10265.612us 1 1 100.00
hmac_same_csr_outstanding 1.830s 140.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.820s 313.562us 1 1 100.00
hmac_tl_intg_err 2.540s 136.303us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.540s 136.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.330s 42.911us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.790s 118.909us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 17.950s 4256.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.790s 35.395us 1 1 100.00